linux-stable.git/drivers/pinctrl, branch v3.16.64

pinctrl: berlin: fix 'pctrl->functions' allocation in berlin_pinctrl_build_state

2018-12-16T22:08:34+00:00

commit b5031b7db77dc47f474f0efc2b2552c32b7bb59d upstream.

fixes following Smatch static check warning:

 drivers/pinctrl/berlin/berlin.c:237 berlin_pinctrl_build_state()
 warn: passing devm_ allocated variable to kfree. 'pctrl->functions'

As we will be calling krealloc() on pointer 'pctrl->functions', which means
kfree() will be called in there, devm_kzalloc() shouldn't be used with
the allocation in the first place.  Fix the warning by calling kcalloc()
and managing the free procedure in error path on our own.

Fixes: 3de68d331c24 ("pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs")
Signed-off-by: YueHaibing 
Reviewed-by: Jisheng Zhang 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16: berlin_pinctrl_state() was not yet converted
 to devm_kcalloc()]
Signed-off-by: Ben Hutchings

pinctrl: freescale: off by one in imx1_pinconf_group_dbg_show()

2018-12-16T22:08:31+00:00

commit 19da44cd33a3a6ff7c97fff0189999ff15b241e4 upstream.

The info->groups[] array is allocated in imx1_pinctrl_parse_dt().  It
has info->ngroups elements.  Thus the > here should be >= to prevent
reading one element beyond the end of the array.

Fixes: 30612cd90005 ("pinctrl: imx1 core driver")
Signed-off-by: Dan Carpenter 
Reviewed-by: Uwe Kleine-König 
Acked-by: Dong Aisheng 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16: adjust filename]
Signed-off-by: Ben Hutchings

pinctrl: imx: off by one in imx_pinconf_group_dbg_show()

2018-12-16T22:08:29+00:00

commit b4859f3edb47825f62d1b2efdd75fe7945996f49 upstream.

The > should really be >= here.  It's harmless because
pinctrl_generic_get_group() will return a NULL if group is invalid.

Fixes: ae75ff814538 ("pinctrl: pinctrl-imx: add imx pinctrl core driver")
Reported-by: Dong Aisheng 
Signed-off-by: Dan Carpenter 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16: adjust filename, context]
Signed-off-by: Ben Hutchings

pinctrl: msm: Fix msm_config_group_get() to be compliant

2018-12-16T22:08:12+00:00

commit 05e0c828955c1cab58dd71a04539442e5375d917 upstream.

If you do this on an sdm845 board:
  cat /sys/kernel/debug/pinctrl/3400000.pinctrl/pinconf-groups

...it looks like nonsense.  For every pin you see listed:
  input bias bus hold, input bias disabled, input bias pull down, input bias pull up

That's because msm_config_group_get() isn't complying with the rules
that pinconf_generic_dump_one() expects.  Specifically for boolean
parameters (anything with a "struct pin_config_item" where has_arg is
false) the function expects that the function should return its value
not through the "config" parameter but should return "0" if the value
is set and "-EINVAL" if the value isn't set.

Let's fix this.

From a quick sample of other pinctrl drivers, it appears to be
tradition to also return 1 through the config parameter for these
boolean parameters when they exist.  I'm not one to knock tradition,
so I'll follow tradition and return 1 in these cases.  While I'm at
it, I'll also continue searching for four leaf clovers, kocking on
wood three times, and trying not to break mirrors.

Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver")
Signed-off-by: Douglas Anderson 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16:
 - Drop change to case PIN_CONFIG_BIAS_BUS_HOLD
 - Adjust filename, context]
Signed-off-by: Ben Hutchings

pinctrl: samsung: Correct EINTG banks order

2018-11-20T18:04:48+00:00

commit 5cf9a338db94cfd570aa2607bef1b30996f188e3 upstream.

All banks with GPIO interrupts should be at beginning of bank array and
without any other types of banks between them.  This order is expected
by exynos_eint_gpio_irq, when doing interrupt group to bank translation.
Otherwise, kernel NULL pointer dereference would happen when trying to
handle interrupt, due to wrong bank being looked up.  Observed on
s5pv210, when trying to handle gpj0 interrupt, where kernel was mapping
it to gpi bank.

Fixes: 023e06dfa688 ("pinctrl: exynos: add exynos5410 SoC specific data")
Fixes: 608a26a7bc04 ("pinctrl: Add s5pv210 support to pinctrl-exynos)
Signed-off-by: Paweł Chmiel 
Reviewed-by: Tomasz Figa 
Signed-off-by: Krzysztof Kozlowski 
[bwh: Backported to 3.16:
 - Drop change to exynos5410_pin_banks0
 - Adjust filename]
Signed-off-by: Ben Hutchings

pinctrl: pinctrl-single: Fix pcs_request_gpio() when bits_per_mux != 0

2018-10-21T07:44:59+00:00

commit 45dcb54f014d3d1f5cc3919b5f0c97087d7cb3dd upstream.

This fixes pcs_request_gpio() in the pinctrl-single driver when
bits_per_mux != 0. It appears this was overlooked when the multiple
pins per register feature was added.

Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: David Lechner 
Acked-by: Tony Lindgren 
Signed-off-by: Linus Walleij 
Signed-off-by: Ben Hutchings

pinctrl: Really force states during suspend/resume

2018-06-16T21:21:45+00:00

commit 981ed1bfbc6c4660b2ddaa8392893e20a6255048 upstream.

In case a platform only defaults a "default" set of pins, but not a
"sleep" set of pins, and this particular platform suspends and resumes
in a way that the pin states are not preserved by the hardware, when we
resume, we would call pinctrl_single_resume() -> pinctrl_force_default()
-> pinctrl_select_state() and the first thing we do is check that the
pins state is the same as before, and do nothing.

In order to fix this, decouple the actual state change from
pinctrl_select_state() and move it pinctrl_commit_state(), while keeping
the p->state == state check in pinctrl_select_state() not to change the
caller assumptions. pinctrl_force_sleep() and pinctrl_force_default()
are updated to bypass the state check by calling pinctrl_commit_state().

[Linus Walleij]
The forced pin control states are currently only used in some pin
controller drivers that grab their own reference to their own pins.
This is equal to the pin control hogs: pins taken by pin control
devices since there are no corresponding device in the Linux device
hierarchy, such as memory controller lines or unused GPIO lines,
or GPIO lines that are used orthogonally from the GPIO subsystem
but pincontrol-wise managed as hogs (non-strict mode, allowing
simultaneous use by GPIO and pin control). For this case forcing
the state from the drivers' suspend()/resume() callbacks makes
sense and should semantically match the name of the function.

Fixes: 6e5e959dde0d ("pinctrl: API changes to support multiple states per device")
Signed-off-by: Florian Fainelli 
Reviewed-by: Andy Shevchenko 
Signed-off-by: Linus Walleij 
Signed-off-by: Ben Hutchings

pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

2017-11-11T13:33:11+00:00

commit d81ece747d8727bb8b1cfc9a20dbe62f09a4e35a upstream.

The PH16 pin has a function with mux id 0x5, which is the DET pin of the
"sim" (smart card reader) IP block.

This function is missing in old versions of A10/A20 SoCs' datasheets and
user manuals, so it's also missing in the old drivers. The newest A10
Datasheet V1.70 and A20 Datasheet V1.41 contain this pin function, and
it's discovered during implementing R40 pinctrl driver.

Add it to the driver. As we now merged A20 pinctrl driver to the A10
one, we need to only fix the A10 driver now.

Fixes: f2821b1ca3a2 ("pinctrl: sunxi: Move Allwinner A10 pinctrl
driver to a driver of its own")

Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij 
Signed-off-by: Ben Hutchings

pinctrl: imx: fix debug message for SHARE_MUX_CONF_REG case

2017-10-12T14:27:43+00:00

commit 66b54e3a5a64925d9819eae86b8f36e90e60037f upstream.

The original implemented debug message does not work for
SHARE_MUX_CONF_REG case. This patch fixes it.

Fixes: bf5a530971af ("pinctrl: imx: add VF610 support to imx pinctrl framework")
Signed-off-by: Dong Aisheng 
Acked-by: Shawn Guo 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16: adjust filename]
Signed-off-by: Ben Hutchings

pinctrl: mxs: atomically switch mux and drive strength config

2017-09-15T17:29:49+00:00

commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 upstream.

To set the mux mode of a pin two bits must be set. Up to now this is
implemented using the following idiom:

	writel(mask, reg + CLR);
	writel(value, reg + SET);

. This however results in the mux mode being 0 between the two writes.

On my machine there is an IC's reset pin connected to LCD_D20. The
bootloader configures this pin as GPIO output-high (i.e. not holding the
IC in reset). When Linux reconfigures the pin to GPIO the short time
LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
the connected IC.

The same problem is present for the pin's drive strength setting which is
reset to low drive strength before using the right value.

So instead of relying on the hardware to modify the register setting
using two writes implement the bit toggling using read-modify-write.

Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
Signed-off-by: Uwe Kleine-König 
Acked-by: Shawn Guo 
Signed-off-by: Linus Walleij 
[bwh: Backported to 3.16: adjust filename, context]
Signed-off-by: Ben Hutchings