<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/drivers/pinctrl/tegra, branch v5.7</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>pinctrl: tegra: Add SFIO/GPIO programming on Tegra194</title>
<updated>2020-03-27T10:46:06+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=368b62f2fd077d4c7db09461e8e24f07491a513d'/>
<id>368b62f2fd077d4c7db09461e8e24f07491a513d</id>
<content type='text'>
Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
of the GPIO controller's register programming. Starting with Tegra186, a
pin is configured as GPIO or SFIO with a bit in a configuration register
of the pin controller.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Prior to Tegra186, the selection of SFIO vs. GPIO modes was done as part
of the GPIO controller's register programming. Starting with Tegra186, a
pin is configured as GPIO or SFIO with a bit in a configuration register
of the pin controller.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-10-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Renumber the GG.0 and GG.1 pins</title>
<updated>2020-03-27T10:44:59+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=103afc8e9e8c4eff96052b311d19f7c32b653ebb'/>
<id>103afc8e9e8c4eff96052b311d19f7c32b653ebb</id>
<content type='text'>
There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
There is no need to define these at a specific offset since they are the
only pins defined for this SoC generation. Begin numbering them at 0.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-9-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Do not add default pin range on Tegra194</title>
<updated>2020-03-27T10:44:30+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=f67499f8ea7c15818d3375d718bd6cde4ae3d4f5'/>
<id>f67499f8ea7c15818d3375d718bd6cde4ae3d4f5</id>
<content type='text'>
On Tegra194, almost all of the pin control programming happens in early
boot firmware, so there is no use in having a pin range defined for all
the pins.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On Tegra194, almost all of the pin control programming happens in early
boot firmware, so there is no use in having a pin range defined for all
the pins.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-8-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Pass struct tegra_pmx for pin range check</title>
<updated>2020-03-27T10:42:32+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=6e01e0c7a0bebd8626e651181d3592cea8d456c4'/>
<id>6e01e0c7a0bebd8626e651181d3592cea8d456c4</id>
<content type='text'>
Pass the struct tegra_pmx when checking for the pin range in device
tree. This makes the call site a bit easier to read and will help keep
that readability in a subsequent patch.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-7-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pass the struct tegra_pmx when checking for the pin range in device
tree. This makes the call site a bit easier to read and will help keep
that readability in a subsequent patch.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-7-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Fix "Scmitt" -&gt; "Schmitt" typo</title>
<updated>2020-03-27T10:41:38+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=66539e6eac708d47b5db8909b08cf9fbeac8a1db'/>
<id>66539e6eac708d47b5db8909b08cf9fbeac8a1db</id>
<content type='text'>
Properly spell "Schmitt" in the kerneldoc for pin group definitions.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Properly spell "Schmitt" in the kerneldoc for pin group definitions.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-6-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Fix whitespace issues for improved readability</title>
<updated>2020-03-27T10:41:04+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-03-19T12:27:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=028e45cda228efdae9d3faad9c4f7bec260ed707'/>
<id>028e45cda228efdae9d3faad9c4f7bec260ed707</id>
<content type='text'>
Fix a few whitespace inconsistencies to make the code easier to read.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-5-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Fix a few whitespace inconsistencies to make the code easier to read.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20200319122737.3063291-5-thierry.reding@gmail.com
Tested-by: Vidya Sagar &lt;vidyas@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: fix missing __iomem in suspend/resume</title>
<updated>2020-01-06T23:01:09+00:00</updated>
<author>
<name>Ben Dooks (Codethink)</name>
<email>ben.dooks@codethink.co.uk</email>
</author>
<published>2019-12-18T11:04:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=4805746420a96011af78437552f5231deef6f295'/>
<id>4805746420a96011af78437552f5231deef6f295</id>
<content type='text'>
The functions should have __iomem on the register pointer
so add that to silence the following sparse warnings:

drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22:    expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22:    got void [noderef] &lt;asn:2&gt; *
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42:    expected void const volatile [noderef] &lt;asn:2&gt; *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42:    got unsigned int [usertype] *
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22:    expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22:    got void [noderef] &lt;asn:2&gt; *
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25:    expected void volatile [noderef] &lt;asn:2&gt; *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25:    got unsigned int [usertype] *

Signed-off-by: Ben Dooks (Codethink) &lt;ben.dooks@codethink.co.uk&gt;
Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The functions should have __iomem on the register pointer
so add that to silence the following sparse warnings:

drivers/pinctrl/tegra/pinctrl-tegra.c:657:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22:    expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:657:22:    got void [noderef] &lt;asn:2&gt; *
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42: warning: incorrect type in argument 1 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42:    expected void const volatile [noderef] &lt;asn:2&gt; *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:659:42:    got unsigned int [usertype] *
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22: warning: incorrect type in assignment (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22:    expected unsigned int [usertype] *regs
drivers/pinctrl/tegra/pinctrl-tegra.c:675:22:    got void [noderef] &lt;asn:2&gt; *
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25: warning: incorrect type in argument 2 (different address spaces)
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25:    expected void volatile [noderef] &lt;asn:2&gt; *addr
drivers/pinctrl/tegra/pinctrl-tegra.c:677:25:    got unsigned int [usertype] *

Signed-off-by: Ben Dooks (Codethink) &lt;ben.dooks@codethink.co.uk&gt;
Link: https://lore.kernel.org/r/20191218110456.2533088-1-ben.dooks@codethink.co.uk
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: use devm_platform_ioremap_resource() to simplify code</title>
<updated>2019-11-05T14:33:40+00:00</updated>
<author>
<name>YueHaibing</name>
<email>yuehaibing@huawei.com</email>
</author>
<published>2019-11-04T14:26:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=4b024225c4a8245e6ecc66ce1df1eaf2ebeb4acb'/>
<id>4b024225c4a8245e6ecc66ce1df1eaf2ebeb4acb</id>
<content type='text'>
devm_platform_ioremap_resource() internally have platform_get_resource()
and devm_ioremap_resource() in it. So instead of calling them separately
use devm_platform_ioremap_resource() directly.

Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Acked-by: Jesper Nilsson &lt;jesper.nilsson@axis.com&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
devm_platform_ioremap_resource() internally have platform_get_resource()
and devm_ioremap_resource() in it. So instead of calling them separately
use devm_platform_ioremap_resource() directly.

Signed-off-by: YueHaibing &lt;yuehaibing@huawei.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
Acked-by: Manivannan Sadhasivam &lt;manivannan.sadhasivam@linaro.org&gt;
Acked-by: Jesper Nilsson &lt;jesper.nilsson@axis.com&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: xusb: Add note about legacy status</title>
<updated>2019-10-04T21:20:04+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>thierry.reding@gmail.com</email>
</author>
<published>2019-09-23T09:54:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9978339ae4e08fd6b7c8200db0fff9dbe6e034d2'/>
<id>9978339ae4e08fd6b7c8200db0fff9dbe6e034d2</id>
<content type='text'>
Add a comment about why the call to of_match_node() cannot be replaced
by of_device_get_match_data(). This will hopefully prevent people from
attempting to clean this up in the future.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a comment about why the call to of_match_node() cannot be replaced
by of_device_get_match_data(). This will hopefully prevent people from
attempting to clean this up in the future.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20190923095400.GA11084@ulmo
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pinctrl: tegra: Flush pinctrl writes during resume</title>
<updated>2019-08-21T07:00:16+00:00</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2019-08-16T19:41:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a4873accca0529b6a32e1ceb458be843cdea9ec6'/>
<id>a4873accca0529b6a32e1ceb458be843cdea9ec6</id>
<content type='text'>
This patch adds pinctrl register read to flush all the prior pinctrl
writes and then adds barrier for pinctrl register read to complete
during resume to make sure all pinctrl changes are effective.

Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds pinctrl register read to flush all the prior pinctrl
writes and then adds barrier for pinctrl register read to complete
during resume to make sure all pinctrl changes are effective.

Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Reviewed-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
