linux-stable.git/drivers/pinctrl/tegra, branch linux-5.4.y

pinctrl: tegra: Use noirq suspend/resume callbacks

2020-06-30T19:37:04+00:00

[ Upstream commit 782b6b69847f34dda330530493ea62b7de3fd06a ]

Use noirq suspend/resume callbacks as other drivers which implement
noirq suspend/resume callbacks (Ex:- PCIe) depend on pinctrl driver to
configure the signals used by their respective devices in the noirq phase.

Signed-off-by: Vidya Sagar 
Reviewed-by: Dmitry Osipenko 
Link: https://lore.kernel.org/r/20200604174935.26560-1-vidyas@nvidia.com
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: tegra: Flush pinctrl writes during resume

2019-08-21T07:00:16+00:00

This patch adds pinctrl register read to flush all the prior pinctrl
writes and then adds barrier for pinctrl register read to complete
during resume to make sure all pinctrl changes are effective.

Acked-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Link: https://lore.kernel.org/r/1565984527-5272-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij

pinctrl: tegra: Fix write barrier placement in pmx_writel

2019-08-21T07:00:16+00:00

pmx_writel uses writel which inserts write barrier before the
register write.

This patch has fix to replace writel with writel_relaxed followed
by a readback and memory barrier to ensure write operation is
completed for successful pinctrl change.

Acked-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Link: https://lore.kernel.org/r/1565984527-5272-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij

pinctrl: tegra210: Add Tegra210 pinctrl pm ops

2019-08-05T09:21:28+00:00

This patch adds suspend and resume functionality to Tegra210 pinctrl.

Signed-off-by: Sowjanya Komatineni 
Link: https://lore.kernel.org/r/1564607463-28802-3-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij

pinctrl: tegra: Add suspend and resume support

2019-08-05T09:19:35+00:00

This patch adds support for Tegra pinctrl driver suspend and resume.

During suspend, context of all pinctrl registers are stored and
on resume they are all restored to have all the pinmux and pad
configuration for normal operation.

Acked-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Sowjanya Komatineni 
Link: https://lore.kernel.org/r/1564607463-28802-2-git-send-email-skomatineni@nvidia.com
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2019-07-13T22:02:27+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.3 kernel cycle:

Core changes:

- Device links can optionally be added between a pin control producer
and its consumers. This will affect how the system power management
is handled: a pin controller will not suspend before all of its
consumers have been suspended.

This was necessary for the ST Microelectronics STMFX expander and
need to be tested on other systems as well: it makes sense to make
this default in the long run.

Right now it is opt-in per driver.

- Drive strength can be specified in microamps. With decreases in
silicon technology, milliamps isn't granular enough, let's make it
possible to select drive strengths in microamps.

Right now the Meson (AMlogic) driver needs this.

New drivers:

- New subdriver for the Tegra 194 SoC.

- New subdriver for the Qualcomm SDM845.

- New subdriver for the Qualcomm SM8150.

- New subdriver for the Freescale i.MX8MN (Freescale is now a product
line of NXP).

- New subdriver for Marvell MV98DX1135.

Driver improvements:

- The Bitmain BM1880 driver now supports pin config in addition to
muxing.

- The Qualcomm drivers can now reserve some GPIOs as taken aside and
not usable for users. This is used in ACPI systems to take out some
GPIO lines used by the BIOS so that noone else (neither kernel nor
userspace) will play with them by mistake and crash the machine.

- A slew of refurbishing around the Aspeed drivers (board management
controllers for servers) in preparation for the new Aspeed AST2600
SoC.

- A slew of improvements over the SH PFC drivers as usual.

- Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
pinctrl: aspeed: Strip moved macros and structs from private header
pinctrl: aspeed: Fix missed include
pinctrl: baytrail: Use GENMASK() consistently
pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
pinctrl: qcom: Add SM8150 pinctrl driver
dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
dt-bindings: pinctrl: qcom: Document missing gpio nodes
pinctrl: aspeed: Add implementation-related documentation
pinctrl: aspeed: Split out pinmux from general pinctrl
pinctrl: aspeed: Clarify comment about strapping W1C
pinctrl: aspeed: Correct comment that is no longer true
MAINTAINERS: Add entry for ASPEED pinctrl drivers
dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
dt-bindings: pinctrl: aspeed: Split bindings document in two
pinctrl: qcom: Add irq_enable callback for msm gpio
pinctrl: madera: Fixup SPDX headers
pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
pinctrl: tegra: Add bitmask support for parked bits
...

pinctrl: tegra: Add bitmask support for parked bits

2019-06-25T13:35:58+00:00

Some pin groups have park bits for multiple pins in one register.
Support this by turning the parked bit field into a parked bitmask
field. If no parked bits are supported, the bitmask can be 0.

Update the pingroup table on Tegra210, which is the only generation
where this is supported, with the parked bitmask.

Signed-off-by: Thierry Reding 
Tested-by: Dmitry Osipenko 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Linus Walleij

pinctrl: tegra: Set specific GPIO compatible string

2019-06-25T13:34:37+00:00

Rather than reuse the nvidia,tegra30-gpio compatible string
to find the GPIO controller on Tegra30, Tegra114, Tegra124 and
Tegra210, use the most specific compatible string for each
SoC generation for consistency.

Signed-off-by: Thierry Reding 
Reviewed-by: Dmitry Osipenko 
Signed-off-by: Linus Walleij

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288

2019-06-05T15:36:37+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 263 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Alexios Zavras 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190529141901.208660670@linutronix.de
Signed-off-by: Greg Kroah-Hartman

pinctrl: tegra: Add Tegra194 pinmux driver

2019-06-01T17:23:06+00:00

Tegra194 has PCIE L5 rst and clkreq pins which need to be controlled
dynamically at runtime. This driver supports change pinmux for these
pins. Pinmux for rest of the pins is set statically by bootloader and
will not be changed by this driver

Signed-off-by: Krishna Yarlagadda 
Signed-off-by: Suresh Mangipudi 
Tested-by: Vidya Sagar 
Signed-off-by: Linus Walleij