linux-stable.git/drivers/pinctrl/sunxi, branch v5.4

pinctrl: sunxi: v3s: introduce support for V3

2019-08-05T10:35:29+00:00

Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.

Signed-off-by: Icenowy Zheng 
Acked-by: Maxime Ripard 

Link: https://lore.kernel.org/r/20190728031227.49140-2-icenowy@aosc.io
Signed-off-by: Linus Walleij

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46+00:00

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

pinctrl: sunxi: Support I/O bias voltage setting on H6

2019-04-23T10:31:42+00:00

H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.

Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).

This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:

  commit 402bfb3c1352 ("Support I/O bias voltage setting on A80")

Signed-off-by: Ondrej Jirman 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Prepare for alternative bias voltage setting methods

2019-04-23T10:29:21+00:00

H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.

Signed-off-by: Ondrej Jirman 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Allow to disable pinctrl drivers

2019-04-04T03:55:54+00:00

Our pinctrl drivers are consisting of some common code, and big pin tables
that are SoC-specific. This is fine in most cases, but when you want to
reduce the size of the particular kernel image, those big tables are, well,
quite big.

We haven't had the option to disable them in the past since they were
hidden Kconfig options based on the SoC support. However, that granularity
isn't great since we don't have one Kconfig option per-SoC, but rather one
by family.

Make those options selectable by the user so that they can disable it if
needed, while keeping the current default to not change the standard case.

Acked-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Declare set_config on the GPIO chip

2019-04-04T03:54:59+00:00

Our pin controller can configure the pins no matter how they are muxed, so
it makes sense to allow this for GPIOs as well.

Add the generic set_config function so that we can rely on the existing
pinctrl code we have.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Fix variable assignment syntax

2019-04-04T03:54:55+00:00

Lines are usually ended with a semi-column in C, yet this was copied from a
structure declaration to the init variant while keeping the comma at the
end. Make sure we have a normal syntax, instead of multiple assignments.

Fixes: d83c82ce7ccd ("pinctrl: sunxi: support multiple pin controller")
Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: implement pin_config_set

2019-04-04T03:54:39+00:00

The sunxi pinctrl only implements the pin_config_group_set callback at the
moment, whereas the gpiochip_generic_config function relies on
pin_config_set. Rework the functions a little to support pin_config_set,
and rely on it for pin_config_group_set.

Signed-off-by: Maxime Ripard 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Support I/O bias voltage setting on A80

2019-02-11T08:20:58+00:00

The A80 SoC has configuration registers for I/O bias voltage. Incorrect
settings would make the affected peripherals inoperable in some cases,
such as Ethernet RGMII signals biased at 2.5V with the settings still
at 3.3V. However low speed signals such as MDIO on the same group of
pins seem to be unaffected.

Previously there was no way to know what the actual voltage used was,
short of hard-coding a value in the device tree. With the new pin bank
regulator supply support in place, the driver can now query the
regulator for its voltage, and if it's valid (as opposed to being the
dummy regulator), set the bias voltage setting accordingly.

Add a quirk to denote the presence of the configuration registers, and
a function to set the correct setting based on the voltage read back
from the regulator.

This is only done when the regulator is first acquired and enabled.
While it would be nice to have a notifier on the regulator so that when
the voltage changes, the driver can update the setting, in practice no
board currently supports dynamic changing of the I/O voltages.

Signed-off-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij

pinctrl: sunxi: Correct number of IRQ banks on H6 main pin controller

2019-01-22T09:52:39+00:00

The H6 main pin controller has four banks of interrupt-triggering pins.
The driver as originally submitted only specified three, but had pin
descriptions referencing a fourth bank. This results in a out-of-bounds
access into .irq_array of struct sunxi_pinctrl. This however did not
result in a crash until v4.20, with commit a66d972465d1 ("devres: Align
data[] to ARCH_KMALLOC_MINALIGN"), which changed the alignment of memory
region returned by devm_kcalloc(). The increase likely moved the
out-of-bounds access into the next, unmapped page.

With KASAN on, the bug is quite clear:

    BUG: KASAN: slab-out-of-bounds in sunxi_pinctrl_init_with_variant+0x49c/0x12b8
    Write of size 4 at addr ffff80002c680280 by task swapper/0/1

    CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.0.0-rc1-00016-gc480a5e6a077 #3
    Hardware name: OrangePi Lite2 (DT)
    Call trace:
     dump_backtrace+0x0/0x220
     show_stack+0x14/0x20
     dump_stack+0xac/0xd4
     print_address_description+0x60/0x25c
     kasan_report+0x14c/0x1ac
     __asan_store4+0x80/0xa0
     sunxi_pinctrl_init_with_variant+0x49c/0x12b8
     h6_pinctrl_probe+0x18/0x20
     platform_drv_probe+0x6c/0xc8
     really_probe+0x244/0x4b0
     driver_probe_device.part.4+0x11c/0x164
     __driver_attach+0x120/0x190
     bus_for_each_dev+0xe8/0x158
     driver_attach+0x30/0x40
     bus_add_driver+0x308/0x318
     driver_register+0xbc/0x1d0
     __platform_driver_register+0x7c/0x88
     h6_pinctrl_driver_init+0x18/0x20
     do_one_initcall+0xd4/0x208
     kernel_init_freeable+0x230/0x2c8
     kernel_init+0x10/0x108
     ret_from_fork+0x10/0x1c

    Allocated by task 1:
     kasan_kmalloc.part.0+0x4c/0x100
     kasan_kmalloc+0xc4/0xe8
     kasan_slab_alloc+0x14/0x20
     __kmalloc_track_caller+0x130/0x238
     devm_kmalloc+0x34/0xd0
     sunxi_pinctrl_init_with_variant+0x1d8/0x12b8
     h6_pinctrl_probe+0x18/0x20
     platform_drv_probe+0x6c/0xc8
     really_probe+0x244/0x4b0
     driver_probe_device.part.4+0x11c/0x164
     __driver_attach+0x120/0x190
     bus_for_each_dev+0xe8/0x158
     driver_attach+0x30/0x40
     bus_add_driver+0x308/0x318
     driver_register+0xbc/0x1d0
     __platform_driver_register+0x7c/0x88
     h6_pinctrl_driver_init+0x18/0x20
     do_one_initcall+0xd4/0x208
     kernel_init_freeable+0x230/0x2c8
     kernel_init+0x10/0x108
     ret_from_fork+0x10/0x1c

    Freed by task 0:
    (stack is not available)

    The buggy address belongs to the object at ffff80002c680080
     which belongs to the cache kmalloc-512 of size 512
    The buggy address is located 0 bytes to the right of
     512-byte region [ffff80002c680080, ffff80002c680280)
    The buggy address belongs to the page:
    page:ffff7e0000b1a000 count:1 mapcount:0 mapping:ffff80002e00c780 index:0xffff80002c683c80 compound_mapcount: 0
    flags: 0x10200(slab|head)
    raw: 0000000000010200 ffff80002e003a10 ffff80002e003a10 ffff80002e00c780
    raw: ffff80002c683c80 0000000000100001 00000001ffffffff 0000000000000000
    page dumped because: kasan: bad access detected

    Memory state around the buggy address:
     ffff80002c680180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
     ffff80002c680200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
    >ffff80002c680280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
		       ^
     ffff80002c680300: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
     ffff80002c680380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc

Correct the number of IRQ banks so there are no more mismatches.

Fixes: c8a830904991 ("pinctrl: sunxi: add support for the Allwinner H6 main pin controller")
Cc: 
Signed-off-by: Chen-Yu Tsai 
Tested-by: Neil Armstrong 
Acked-by: Maxime Ripard 
Signed-off-by: Linus Walleij