linux-stable.git/drivers/pinctrl/stm32, branch linux-5.18.y

pinctrl: stm32: fix optional IRQ support to gpios

2022-07-29T15:27:55+00:00

commit a1d4ef1adf8bbd302067534ead671a94759687ed upstream.

To act as an interrupt controller, a gpio bank relies on the
"interrupt-parent" of the pin controller.
When this optional "interrupt-parent" misses, do not create any IRQ domain.

This fixes a "NULL pointer in stm32_gpio_domain_alloc()" kernel crash when
the interrupt-parent =  property is not declared in the Device Tree.

Fixes: 0eb9f683336d ("pinctrl: Add IRQ support to STM32 gpios")
Signed-off-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20220627142350.742973-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: stm32: Keep pinctrl block clock enabled when LEVEL IRQ requested

2022-04-22T22:10:11+00:00

The current EOI handler for LEVEL triggered interrupts calls clk_enable(),
register IO, clk_disable(). The clock manipulation requires locking which
happens with IRQs disabled in clk_enable_lock(). Instead of turning the
clock on and off all the time, enable the clock in case LEVEL interrupt is
requested and keep the clock enabled until all LEVEL interrupts are freed.
The LEVEL interrupts are an exception on this platform and seldom used, so
this does not affect the common case.

This simplifies the LEVEL interrupt handling considerably and also fixes
the following splat found when using preempt-rt:
 ------------[ cut here ]------------
 WARNING: CPU: 0 PID: 0 at kernel/locking/rtmutex.c:2040 __rt_mutex_trylock+0x37/0x62
 Modules linked in:
 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.10.109-rt65-stable-standard-00068-g6a5afc4b1217 #85
 Hardware name: STM32 (Device Tree Support)
 [] (unwind_backtrace) from [] (show_stack+0xb/0xc)
 [] (show_stack) from [] (dump_stack+0x6f/0x84)
 [] (dump_stack) from [] (__warn+0x7f/0xa4)
 [] (__warn) from [] (warn_slowpath_fmt+0x3b/0x74)
 [] (warn_slowpath_fmt) from [] (__rt_mutex_trylock+0x37/0x62)
 [] (__rt_mutex_trylock) from [] (rt_spin_trylock+0x7/0x16)
 [] (rt_spin_trylock) from [] (clk_enable_lock+0xb/0x80)
 [] (clk_enable_lock) from [] (clk_core_enable_lock+0x9/0x18)
 [] (clk_core_enable_lock) from [] (stm32_gpio_get+0x11/0x24)
 [] (stm32_gpio_get) from [] (stm32_gpio_irq_trigger+0x1f/0x48)
 [] (stm32_gpio_irq_trigger) from [] (handle_fasteoi_irq+0x71/0xa8)
 [] (handle_fasteoi_irq) from [] (generic_handle_irq+0x19/0x22)
 [] (generic_handle_irq) from [] (__handle_domain_irq+0x55/0x64)
 [] (__handle_domain_irq) from [] (gic_handle_irq+0x53/0x64)
 [] (gic_handle_irq) from [] (__irq_svc+0x65/0xc0)
 Exception stack(0xc0e01f18 to 0xc0e01f60)
 1f00:                                                       0000300c 00000000
 1f20: 0000300c c010ff01 00000000 00000000 c0e00000 c0e07714 00000001 c0e01f78
 1f40: c0e07758 00000000 ef7cd0ff c0e01f68 c010554b c0105542 40000033 ffffffff
 [] (__irq_svc) from [] (arch_cpu_idle+0xc/0x1e)
 [] (arch_cpu_idle) from [] (default_idle_call+0x21/0x3c)
 [] (default_idle_call) from [] (do_idle+0xe3/0x1e4)
 [] (do_idle) from [] (cpu_startup_entry+0x13/0x14)
 [] (cpu_startup_entry) from [] (start_kernel+0x397/0x3d4)
 [] (start_kernel) from [<00000000>] (0x0)
 ---[ end trace 0000000000000002 ]---

Power consumption measured on STM32MP157C DHCOM SoM is not increased or
is below noise threshold.

Fixes: 47beed513a85b ("pinctrl: stm32: Add level interrupt support to gpio irq chip")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Fabien Dessenne 
Cc: Linus Walleij 
Cc: Marc Zyngier 
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
To: linux-gpio@vger.kernel.org
Reviewed-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20220421140827.214088-1-marex@denx.de
Signed-off-by: Linus Walleij

pinctrl: stm32: Do not call stm32_gpio_get() for edge triggered IRQs in EOI

2022-04-21T14:30:30+00:00

The stm32_gpio_get() should only be called for LEVEL triggered interrupts,
skip calling it for EDGE triggered interrupts altogether to avoid wasting
CPU cycles in EOI handler. On this platform, EDGE triggered interrupts are
the majority and LEVEL triggered interrupts are the exception no less, and
the CPU cycles are not abundant.

Fixes: 47beed513a85b ("pinctrl: stm32: Add level interrupt support to gpio irq chip")
Signed-off-by: Marek Vasut 
Cc: Alexandre Torgue 
Cc: Fabien Dessenne 
Cc: Linus Walleij 
Cc: Marc Zyngier 
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
To: linux-gpio@vger.kernel.org
Link: https://lore.kernel.org/r/20220415215410.498349-1-marex@denx.de
Signed-off-by: Linus Walleij

pinctrl: stm32: consider the GPIO offset to expose all the GPIO lines

2021-12-16T03:14:56+00:00

Consider the GPIO controller offset (from "gpio-ranges") to compute the
maximum GPIO line number.
This fixes an issue where gpio-ranges uses a non-null offset.
  e.g.: gpio-ranges = <&pinctrl 6 86 10>
        In that case the last valid GPIO line is not 9 but 15 (6 + 10 - 1)

Cc: stable@vger.kernel.org
Fixes: 67e2996f72c7 ("pinctrl: stm32: fix the reported number of GPIO lines per bank")
Reported-by: Christoph Fritz 
Signed-off-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20211215095808.621716-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2021-11-05T15:24:17+00:00

Pull pin control updates from Linus Walleij:
 "The most interesting aspect is that we now have initial support for
  the Apple pin controller as used in the M1 laptops and the iPhones
  which is a step forward for using Linux efficiently on this Apple
  silicon.

  Core changes:

   - Add infrastructure for per-parent interrupt data to support the
     Apple pin controller.

  New drivers:

   - New combined pin control and GPIO driver for the Apple SoC. This is
     used in all modern Apple silicon such as the M1 laptops but also in
     at least recent iPhone variants.

   - New subdriver for the Qualcomm SM6350

   - New subdriver for the Qualcomm QCM2290

   - New subdriver for the Qualcomm PM6350

   - New subdriver for the Uniphier NX1

   - New subdriver for the Samsung ExynosAutoV9

   - New subdriver for the Mediatek MT7986

   - New subdriver for the nVidia Tegra194

  Improvements:

   - Improve power management in the Mediatek driver.

   - Improvements to the Renesas internal consistency checker.

   - Convert the Rockchip pin control device tree bindings to YAML.

   - Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO driver to
     use hierarchical interrupts.

   - Convert the Qualcomm PMIC MPP device tree bindings to YAML"

* tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (55 commits)
  pinctrl: add pinctrl/GPIO driver for Apple SoCs
  dt-bindings: pinctrl: Add apple,npins property to apple,pinctrl
  dt-bindings: pinctrl: add #interrupt-cells to apple,pinctrl
  gpio: Allow per-parent interrupt data
  pinctrl: tegra: Fix warnings and error
  pinctrl: intel: Kconfig: Add configuration menu to Intel pin control
  pinctrl: tegra: Use correct offset for pin group
  pinctrl: core: fix possible memory leak in pinctrl_enable()
  pinctrl: bcm2835: Allow building driver as a module
  pinctrl: equilibrium: Fix function addition in multiple groups
  pinctrl: tegra: Add pinmux support for Tegra194
  pinctrl: tegra: include lpdr pin properties
  pinctrl: mediatek: add support for MT7986 SoC
  dt-bindings: pinctrl: update bindings for MT7986 SoC
  pinctrl: microchip sgpio: use reset driver
  dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset binding
  dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells
  pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip
  pinctrl: qcom: spmi-mpp: hardcode IRQ counts
  pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip
  ...

pinctrl: stm32: use valid pin identifier in stm32_pinctrl_resume()

2021-10-13T23:16:12+00:00

When resuming from low power, the driver attempts to restore the
configuration of some pins. This is done by a call to:
  stm32_pinctrl_restore_gpio_regs(struct stm32_pinctrl *pctl, u32 pin)
where 'pin' must be a valid pin value (i.e. matching some 'groups->pin').
Fix the current implementation which uses some wrong 'pin' value.

Fixes: e2f3cf18c3e2 ("pinctrl: stm32: add suspend/resume management")
Signed-off-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20211008122517.617633-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij

pinctrl: stm32: do not warn when 'st,package' is absent

2021-10-13T23:14:58+00:00

Since the 'st,package' property is optional, outputting the "No package
detected" warning-level log when the property is absent is unsuitable.
Remove that log.

Signed-off-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20211008122454.617556-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij

pinctrl: stm32: Add STM32MP135 SoC support

2021-08-10T12:45:27+00:00

STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO
banks contain same features as STM32MP157 GPIO banks except that
each GPIO line of the STM32MP135 can be secured.

Signed-off-by: Alexandre Torgue 
Acked-by: Arnd Bergmann

Merge tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2021-07-01T23:57:14+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.14 kernel. Not so
much going on. No core changes, just drivers.

The most interesting would be that MIPS Ralink is migrating to pin
control and we have some bindings but not yet code for the Apple M1
pin controller.

New drivers:

- Last merge window we created a driver for the Ralink RT2880. We are
now moving the Ralink SoC pin control drivers out of the MIPS
architecture code and into the pin control subsystem. This concerns
RT288X, MT7620, RT305X, RT3883 and MT7621.

- Qualcomm SM6125 SoC pin control driver.

- Qualcomm spmi-gpio support for PM7325.

- Qualcomm spmi-mpp also handles PMI8994 (just a compatible string)

- Mediatek MT8365 SoC pin controller.

- New device HID for the AMD GPIO controller.

Improvements:

- Pin bias config support for a slew of Renesas pin controllers.

- Incremental improvements and non-urgent bug fixes to the Renesas
SoC drivers.

- Implement irq_set_wake on the AMD pin controller so we can wake up
from external pin events.

Misc:

- Devicetree bindings for the Apple M1 pin controller, we will
probably see a proper driver for this soon as well"

* tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits)
pinctrl: ralink: rt305x: add missing include
pinctrl: stm32: check for IRQ MUX validity during alloc()
pinctrl: zynqmp: some code cleanups
drivers: qcom: pinctrl: Add pinctrl driver for sm6125
dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver
dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios
pinctrl: mcp23s08: Add optional reset GPIO
pinctrl: mediatek: fix mode encoding
pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq()
pinctrl: bcm: Constify static pinmux_ops
pinctrl: bcm: Constify static pinctrl_ops
pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file
pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file
pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file
pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file
pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file
pinctrl: ralink: move ralink architecture pinmux header into the driver
pinctrl: single: config: enable the pin's input
pinctrl: mtk: Fix mt8365 Kconfig dependency
pinctrl: mcp23s08: fix race condition in irq handler
...

pinctrl: stm32: check for IRQ MUX validity during alloc()

2021-06-25T23:52:35+00:00

Considering the following irq_domain_ops call chain:
- .alloc() is called when a clients calls platform_get_irq() or
  gpiod_to_irq()
- .activate() is called next, when the clients calls
  request_threaded_irq()
Check for the IRQ MUX conflict during the first stage (alloc instead of
activate). This avoids to provide the client with an IRQ that can't be
used.

Signed-off-by: Fabien Dessenne 
Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com
Signed-off-by: Linus Walleij