[ Upstream commit 09c816e5c4d3a8d6d6e4b7537433e5e98505d934 ]
spacemit_pin_set_config() looks up the per-pin descriptor with
spacemit_get_pin() then checks the wrong variable for failure:
const struct spacemit_pin *spin = spacemit_get_pin(pctrl, pin);
...
if (!pin)
return -EINVAL;
reg = spacemit_pin_to_reg(pctrl, spin->pin);
pin is an unsigned int pin id, where 0 (GPIO_0 / gmac0_rxdv on K3) is a
valid pin, so rejecting it here drops the PAD config write for the first
pin of every group. On K3 Pico-ITX the GMAC RGMII group lists pin 0 as
its first entry, so its drive-strength / bias configuration was silently
ignored.
The intended guard is against spacemit_get_pin() returning NULL when the
pin id isn't in the SoC's pin table. Check spin instead, which both
restores PAD setup for pin 0 and prevents a NULL deref on spin->pin.
Fixes: a83c29e1d145 ("pinctrl: spacemit: add support for SpacemiT K1 SoC")
Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Return -ENOTSUPP instead of -EINVAL when encountering unsupported pin configuration parameters. This is more logical and allows the GPIO subsystem to gracefully handle unsupported parameters via functions like gpio_set_config_with_argument_optional(), which specifically ignores -ENOTSUPP but treats others as failure. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
This was done entirely with mindless brute force, using
git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'
to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.
Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.
For the same reason the 'flex' versions will be done as a separate
conversion.
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This is the result of running the Coccinelle script from scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to avoid scalar types (which need careful case-by-case checking), and instead replace kmalloc-family calls that allocate struct or union object instances: Single allocations: kmalloc(sizeof(TYPE), ...) are replaced with: kmalloc_obj(TYPE, ...) Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...) are replaced with: kmalloc_objs(TYPE, COUNT, ...) Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...) are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...) (where TYPE may also be *VAR) The resulting allocations no longer return "void *", instead returning "TYPE *". Signed-off-by: Kees Cook <kees@kernel.org>
Dual-voltage GPIO banks default to 3.3V operation. Even when a bank is externally supplied with 1.8V, the internal logic remains in the 3.3V domain, leading to functional failures. Add support for programming the IO domain power control registers to allow explicit configuration for 1.8V operation. These registers are secure due to hardware safety constraints. Specifically, configuring the domain for 1.8V while externally supplying 3.3V causes back-powering and potential pin damage. Consequently, access requires unlocking the AIB Secure Access Register (ASAR) in the APBC block before any read or write operation. Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Signed-off-by: Linus Walleij <linusw@kernel.org>
K3 SoC expand drive strength to 4 bits which support even larger settings table comparing to old SoC generation. Also schmitter trigger setting is changed to 1 bit. Signed-off-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
For the pinctrl IP of SpacemiT's K3 SoC, it has different register offset comparing with previous SoC generation, so introduce a function to do the pin to offset mapping. Also add all the pinctrl data. Signed-off-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
The datasheet lists this signal as PRI_TDI, not PRI_DTI. Fix the pin name to match the documentation and JTAG naming convention (TDI = Test Data In). Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The debug output for spacemit_pinconf_dbg_show() prints an extra newline at the end. This is redundant as pinconf_pins_show() in pinconf.c already adds a newline in its for loop. Remove the newline to avoid the extra line in the output. Example current output: $ cat /sys/kernel/debug/pinctrl/d401e000.pinctrl/pinconf-pins Pin config settings per pin Format: pin (name): configs pin 0 (GPIO_00): , bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) pin 1 (GPIO_01): slew rate (0x0), bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) pin 2 (GPIO_02): slew rate (0x0), bias pull disabled, io type (Fixed/1V8), drive strength (32 mA), register (0x1041) ... Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@hammernet.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20250805150701.129113-1-hendrik.hamerlinck@hammernet.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
For SpacemiT K1 SoC's pinctrl, explicitly acquiring clocks in the driver instead of relying on bootloader or default hardware settings to enable it. Signed-off-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/20250416-02-k1-pinctrl-clk-v2-2-2b5fcbd4183c@gentoo.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>