linux-stable.git/drivers/pinctrl/qcom, branch v6.6.2

pinctrl: qcom: lpass-lpi: fix concurrent register updates

2023-10-16T12:56:49+00:00

The Qualcomm LPASS LPI pin controller driver uses one lock for guarding
Read-Modify-Write code for slew rate registers.  However the pin
configuration and muxing registers have exactly the same RMW code but
are not protected.

Pin controller framework does not provide locking here, thus it is
possible to trigger simultaneous change of pin configuration registers
resulting in non-atomic changes.

Protect from concurrent access by re-using the same lock used to cover
the slew rate register.  Using the same lock instead of adding second
one will make more sense, once we add support for newer Qualcomm SoC,
where slew rate is configured in the same register as pin
configuration/muxing.

Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Cc: stable@vger.kernel.org
Reviewed-by: Linus Walleij 
Signed-off-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20231013145705.219954-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2023-08-31T02:36:19+00:00

Pull pin control updates from Linus Walleij:
 "We have some patches to DTS[I] files in arm and arm64 as well, that
  were merged here as DT headers were being changed.

  The most interesting stuff is the Intel Tangier chip support and
  AMLogic C3 in my opinion.

  No core changes this time.

  Drivers:

   - Intel Tangier SoC pin control support

   - AMLogic C3 SoC pin control support

   - Texas Instruments AM654 SoC pin control support

   - Qualcomm SM8350 and SM6115 LPASS (Low Power Audio Sub-System) pin
     control support

   - Qualcomm PMX75 and PM7550BA (Power Management) pin control support

   - Qualcomm PMC8180 and PMC8180C (Power Management) pin control
     support

   - DROP the Oxnas driver as there is not enough of community interest
     to keep carrying this ARM(11) port

  Enhancements:

   - Bias control in the MT7986 pin control driver

   - Misc device tree binding enhancements such as the Broadcom 11351
     being converted to YAML

   - New macro: DEFINE_NOIRQ_DEV_PM_OPS() put to use

   - Clean up some SPDX headers

   - Handle non-unique devicetree subnode names in two Renesas drivers"

* tag 'pinctrl-v6.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl: mlxbf3: Remove gpio_disable_free()
  pinctrl: use capital "OR" for multiple licenses in SPDX
  dt-bindings: pinctrl: renesas,rza2: Use 'additionalProperties' for child nodes
  pinctrl: cherryview: fix address_space_handler() argument
  pinctrl: intel: consolidate ACPI dependency
  pinctrl: tegra: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: renesas: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mvebu: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: at91: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: cherryview: Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
  pm: Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
  pinctrl: mediatek: assign functions to configure pin bias on MT7986
  pinctrl: mediatek: fix pull_type data for MT7981
  dt-bindings: pinctrl: aspeed: Allow only defined pin mux node properties
  dt-bindings: pinctrl: Drop 'phandle' properties
  pinctrl: lynxpoint: Make use of pm_ptr()
  pinctrl: baytrail: Make use of pm_ptr()
  pinctrl: intel: Switch to use exported namespace
  pinctrl: lynxpoint: reuse common functions from pinctrl-intel
  pinctrl: cherryview: reuse common functions from pinctrl-intel
  ...

Merge tag 'qcom-pinctrl-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into devel

2023-08-15T09:09:06+00:00

Qualcomm pinctrl changes for v6.6

1. Add support for the SM6115 and SM8350 LPASS (Low Power Audio
   SubSystem) TLMM pin controllers.

2. Add bindings for the Qualcomm PMC8180 and PMC8180C PMICs GPIO pin
   controllers.

Signed-off-by: Linus Walleij

pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets

2023-08-10T08:48:15+00:00

SA8775 and newer target have added support for an increased number of
interrupt targets. To implement this change, the intr_target field, which
is used to configure the interrupt target in the interrupt configuration
register is increased from 3 bits to 4 bits.

In accordance to these updates, a new intr_target_width member is
introduced in msm_pingroup structure. This member stores the value of
width of intr_target field in the interrupt configuration register. This
value is used to dynamically calculate and generate mask for setting the
intr_target field. By default, this mask is set to 3 bit wide, to ensure
backward compatibility with the older targets.

Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms")
Tested-by: Andrew Halaney  # sa8775p-ride
Signed-off-by: Ninad Naik 
Reviewed-by: Konrad Dybcio 
Reviewed-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com
Signed-off-by: Linus Walleij

pinctrl: qcom: Remove the unused _groups variable build warning

2023-08-07T09:01:31+00:00

When building with clang toolchain and arm64-randconfig-r015-20230712
kernel test robot reports the below warning.

 drivers/pinctrl/qcom/pinctrl-ipq5018.c:244:27: warning: unused variable '_groups' [-Wunused-const-variable]
   static const char * const _groups[] = {
                             ^
   1 warning generated.

     static const char * const _groups[] = {
             "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
             "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
             "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
             "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
             "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
             "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
             "gpio43", "gpio44", "gpio45", "gpio46",
   };

Fixing it by removing the variable.

Reported-by: kernel test robot 
Closes: https://lore.kernel.org/oe-kbuild-all/202307120814.vWPY6URk-lkp@intel.com/
Fixes: 725d1c891658 ("pinctrl: qcom: Add IPQ5018 pinctrl driver")
Signed-off-by: Sricharan Ramabadhran 
Reviewed-by: Nick Desaulniers 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/1689934361-32642-1-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

2023-08-07T08:51:45+00:00

Add support for the pin controller block on SM6115's Low Power Island.

Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce SM6115 LPI pinctrl driver

2023-07-26T09:09:47+00:00

Add support for the pin controller block on SM6115's Low Power Island.

Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.org
Signed-off-by: Krzysztof Kozlowski

pinctrl: qcom: sm8350-lpass-lpi: add SM8350 LPASS TLMM

2023-07-24T19:07:04+00:00

Add driver for pin controller in Low Power Audio SubSystem (LPASS).  The
driver is similar to SM8250 LPASS pin controller, with difference in one
new pin (gpio14) belonging to swr_tx_data.

Link: https://lore.kernel.org/r/20230719192058.433517-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski

pinctrl: Explicitly include correct DT includes

2023-07-20T19:41:24+00:00

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring 
Reviewed-by: Damien Le Moal 
Acked-by: Emil Renner Berthing 
Acked-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org
Signed-off-by: Linus Walleij

pinctrl: qcom: lpass-lpi: Make the clocks optional, always

2023-07-20T19:37:42+00:00

Some platforms provide a single clock source to all LPASS peripherals,
others provide two, and there are probably others that provide it through
magic invisible-to-Linux wires.

Rely on bindings to mandate the adequate number of clocks necessary.

Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.org
Signed-off-by: Linus Walleij