linux-stable.git/drivers/pinctrl/qcom, branch v5.10

pinctrl: qcom: sm8250: Specify PDC map

2020-11-10T13:57:05+00:00

Specify the PDC mapping for SM8250, so that gpio interrupts are
propertly mapped to the wakeup IRQs of the PDC.

Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20201028043642.1141723-1-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback

2020-11-10T13:30:42+00:00

When GPIOs that are routed to PDC are used as output they can still latch
the IRQ pending at GIC. As a result the spurious IRQ was handled when the
client driver change the direction to input to starts using it as IRQ.

Currently such erroneous latched IRQ are cleared with .irq_enable callback
however if the driver continue to use GPIO as interrupt and invokes
disable_irq() followed by enable_irq() then everytime during enable_irq()
previously latched interrupt gets cleared.

This can make edge IRQs not seen after enable_irq() if they had arrived
after the driver has invoked disable_irq() and were pending at GIC.

Move clearing erroneous IRQ to .irq_request_resources callback as this is
the place where GPIO direction is changed as input and its locked as IRQ.

While at this add a missing check to invoke msm_gpio_irq_clear_unmask()
from .irq_enable callback only when GPIO is not routed to PDC.

Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah 
Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-10-14T22:25:04+00:00

Pull pin control updates from Linus Walleij:
 "Core changes:

   - NONE whatsoever, we don't even touch the core files this time
     around.

  New drivers:

   - New driver for the Toshiba Visconti SoC.

   - New subdriver for the Qualcomm MSM8226 SoC.

   - New subdriver for the Actions Semiconductor S500 SoC.

   - New subdriver for the Mediatek MT8192 SoC.

   - New subdriver for the Microchip SAMA7G5 SoC.

  Driver enhancements:

   - Intel Cherryview and Baytrail cleanups and refactorings.

   - Enhanced support for the Renesas R8A7790, more pins and groups.

   - Some optimizations for the MCP23S08 MCP23x17 variant.

   - Some cleanups around the Actions Semiconductor subdrivers.

   - A bunch of cleanups around the SH-PFC and Emma Mobile drivers.

   - The "SH-PFC" (literally SuperH pin function controller, I think)
     subdirectory is now renamed to the more neutral "renesas", as these
     are not very much centered around SuperH anymore.

   - Non-critical fixes for the Aspeed driver.

   - Non-critical fixes for the Ingenic (MIPS!) driver.

   - Fix a bunch of missing pins on the AMD pinctrl driver"

* tag 'pinctrl-v5.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (78 commits)
  pinctrl: amd: Add missing pins to the pin group list
  dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks
  pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI
  pinctrl: mediatek: Free eint data on failure
  pinctrl: single: fix debug output when #pinctrl-cells = 2
  pinctrl: single: fix pinctrl_spec.args_count bounds check
  pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent
  pinctrl: cannonlake: Modify COMMUNITY macros to be consistent
  pinctrl: tigerlake: Fix register offsets for TGL-H variant
  pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2
  pinctrl: mediatek: use devm_platform_ioremap_resource_byname()
  pinctrl: nuvoton: npcm7xx: Constify static ops structs
  pinctrl: mediatek: mt7622: add antsel pins/groups
  pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register()
  pinctrl: at91-pio4: add support for sama7g5 SoC
  dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5
  pinctrl: spear: simplify the return expression of tvc_connect()
  pinctrl: spear: simplify the return expression of spear310_pinctrl_probe
  pinctrl: sprd: use module_platform_driver to simplify the code
  pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs.
  ...

Merge tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2020-10-12T18:34:32+00:00

Pull irq updates from Thomas Gleixner:
 "Updates for the interrupt subsystem:

  Core:
   - Allow trimming of interrupt hierarchy to support odd hardware
     setups where only a subset of the interrupts requires the full
     hierarchy.

   - Allow the retrigger mechanism to follow a hierarchy to simplify
     driver code.

   - Provide a mechanism to force enable wakeup interrrupts on suspend.

   - More infrastructure to handle IPIs in the core code

  Architectures:
   - Convert ARM/ARM64 IPI handling to utilize the interrupt core code.

  Drivers:
   - The usual pile of new interrupt chips (MStar, Actions Owl, TI
     PRUSS, Designware ICTL)

   - ARM(64) IPI related conversions

   - Wakeup support for Qualcom PDC

   - Prevent hierarchy corruption in the NVIDIA Tegra driver

   - The usual small fixes, improvements and cleanups all over the
     place"

* tag 'irq-core-2020-10-12' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (59 commits)
  dt-bindings: interrupt-controller: Add MStar interrupt controller
  irqchip/irq-mst: Add MStar interrupt controller support
  soc/tegra: pmc: Don't create fake interrupt hierarchy levels
  soc/tegra: pmc: Allow optional irq parent callbacks
  gpio: tegra186: Allow optional irq parent callbacks
  genirq/irqdomain: Allow partial trimming of irq_data hierarchy
  irqchip/qcom-pdc: Reset PDC interrupts during init
  irqchip/qcom-pdc: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
  pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
  genirq/PM: Introduce IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag
  pinctrl: qcom: Use return value from irq_set_wake() call
  pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags
  ARM: Handle no IPI being registered in show_ipi_list()
  MAINTAINERS: Add entries for Actions Semi Owl SIRQ controller
  irqchip: Add Actions Semi Owl SIRQ controller
  dt-bindings: interrupt-controller: Add Actions SIRQ controller binding
  dt-bindings: dw-apb-ictl: Update binding to describe use as primary interrupt controller
  irqchip/dw-apb-ictl: Add primary interrupt controller support
  irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains
  genirq: Add stub for set_handle_irq() when !GENERIC_IRQ_MULTI_HANDLER
  ...

pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag

2020-10-06T10:26:34+00:00

Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the
wakeirqs during suspend entry.

Signed-off-by: Maulik Shah 
Signed-off-by: Marc Zyngier 
Tested-by: Stephen Boyd 
Reviewed-by: Stephen Boyd 
Reviewed-by: Douglas Anderson 
Acked-by: Linus Walleij 
Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org

pinctrl: qcom: Use return value from irq_set_wake() call

2020-10-06T10:23:14+00:00

msmgpio irqchip was not using return value of irq_set_irq_wake() callback
since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor
it implemented .irq_set_wake callback. This lead to irq_set_irq_wake()
return error -ENXIO.

However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be
configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE
flag.

Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent()
instead of always returning success.

Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah 
Signed-off-by: Marc Zyngier 
Tested-by: Stephen Boyd 
Reviewed-by: Douglas Anderson 
Reviewed-by: Stephen Boyd 
Acked-by: Bjorn Andersson 
Acked-by: Linus Walleij 
Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org

pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags

2020-10-06T10:23:13+00:00

Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already
set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked
during suspend or during setting irq type since genirq checks irqchip flag
of msmgpio irqchip which forwards these calls to its parent PDC irqchip.

Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during
suspend and mask before setting irq type. Masking before changing type make
sures any spurious interrupt is not detected during this operation.

Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Maulik Shah 
Signed-off-by: Marc Zyngier 
Tested-by: Stephen Boyd 
Reviewed-by: Douglas Anderson 
Acked-by: Bjorn Andersson 
Acked-by: Linus Walleij 
Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org

pinctrl: qcom: sm8250: correct sdc2_clk

2020-10-01T07:51:16+00:00

Correct sdc2_clk pin definition (register offset is wrong, verified by
the msm-4.19 driver).

Fixes: 4e3ec9e407ad ("pinctrl: qcom: Add sm8250 pinctrl driver.")
Signed-off-by: Dmitry Baryshkov 
Reviewed-by: Bjorn Andersson 
Acked-by: Manivannan Sadhasivam 
Link: https://lore.kernel.org/r/20200914091846.55204-1-dmitry.baryshkov@linaro.org
Signed-off-by: Linus Walleij

pinctrl: qcom: Add msm8226 pinctrl driver.

2020-08-27T08:27:14+00:00

Add initial Qualcomm msm8226 pinctrl driver to support pin configuration
with pinctrl framework for msm8226 SoC.

- Initial formatting and style was taken from the msm8x74 pinctrl driver
  added by Björn Andersson 

Signed-off-by: Bartosz Dudziak 
Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-08-09T19:52:28+00:00

Pull pin control updates from Linus Walleij:
"This is the bulk of the pin control changes for the v5.9 kernel
series:

Core changes:

- The GPIO patch "gpiolib: Introduce for_each_requested_gpio_in_range()
macro" was put in an immutable branch and merged into the pinctrl
tree as well. We see these changes also here.

- Improved debug output for pins used as GPIO.

New drivers:

- Ocelot Sparx5 SoC driver.

- Intel Emmitsburg SoC subdriver.

- Intel Tiger Lake-H SoC subdriver.

- Qualcomm PM660 SoC subdriver.

- Renesas SH-PFC R8A774E1 subdriver.

Driver improvements:

- Linear improvement and cleanups of the Intel drivers for
Cherryview, Lynxpoint, Baytrail etc. Improved locking among other
things.

- Renesas SH-PFC has added support for RPC pins, groups, and
functions to r8a77970 and r8a77980.

- The newere Freescale (now NXP) i.MX8 pin controllers have been
modularized. This is driven by the Google Android GKI initiative I
think.

- Open drain support for pins on the Qualcomm IPQ4019.

- The Ingenic driver can handle both edges IRQ detection.

- A big slew of documentation fixes all over the place.

- A few irqchip template conversions by yours truly.

* tag 'pinctrl-v5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
pinctrl: stmfx: Use irqchip template
pinctrl: amd: Use irqchip template
pinctrl: mediatek: fix build for tristate changes
pinctrl: samsung: Use bank name as irqchip name
pinctrl: core: print gpio in pins debugfs file
pinctrl: mediatek: add mt6779 eint support
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: stm32: use the hwspin_lock_timeout_in_atomic() API
pinctrl: mcp23s08: Use irqchip template
pinctrl: sx150x: Use irqchip template
dt-bindings: ingenic,pinctrl: Support pinmux/pinconf nodes
pinctrl: intel: Add Intel Emmitsburg pin controller support
pinctl: ti: iodelay: Replace HTTP links with HTTPS ones
Revert "gpio: omap: handle pin config bias flags"
pinctrl: single: Use fallthrough pseudo-keyword
pinctrl: qcom: spmi-gpio: Use fallthrough pseudo-keyword
pinctrl: baytrail: Use fallthrough pseudo-keyword
...