linux-stable.git/drivers/pinctrl/meson, branch v5.4 Linux kernel stable tree pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c 2019-09-13T12:40:41+00:00 Otto Meier gf435@gmx.net 2019-09-10T16:01:41+00:00 cb0438e4436085d89706b5ccfce4d5da531253de Hi i tried to use the uart_C of the the odroid-c2. I enabled it in the dts file. During boot it crashed when the the sdcard slot is addressed. After long search in the net i found this: https://forum.odroid.com/viewtopic.php?f=139&t=25371&p=194370&hilit=uart_C#p177856 After changing the pin definitions accordingly erverything works. Uart_c is functioning and sdcard ist working. Fixes: 6db0f3a8a04e46 ("pinctrl: amlogic: gxbb: add more UART pins") Signed-off-by: Otto Meier <gf435@gmx.net> Link: https://lore.kernel.org/r/1cc32a18-464d-5531-7a1c-084390e2ecb1@gmx.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Hi i tried to use the uart_C of the the odroid-c2.

I enabled it in the dts file. During boot it crashed when the
the sdcard slot is addressed.

After long search in the net i found this:

https://forum.odroid.com/viewtopic.php?f=139&t=25371&p=194370&hilit=uart_C#p177856

After changing the pin definitions accordingly erverything works.
Uart_c is functioning and sdcard ist working.

Fixes: 6db0f3a8a04e46 ("pinctrl: amlogic: gxbb: add more UART pins")
Signed-off-by: Otto Meier <gf435@gmx.net>
Link: https://lore.kernel.org/r/1cc32a18-464d-5531-7a1c-084390e2ecb1@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: meson: Add of_node_put() before return 2019-08-23T09:48:08+00:00 Nishka Dasgupta nishkadg.linux@gmail.com 2019-08-15T06:07:18+00:00 2ff110bbe98e2beeb6488021fb650b1afc736263 Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com> Link: https://lore.kernel.org/r/20190815060718.3286-1-nishkadg.linux@gmail.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Each iteration of for_each_child_of_node puts the previous node, but in
the case of a return from the middle of the loop, there is no put, thus
causing a memory leak. Hence add an of_node_put before the return.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lore.kernel.org/r/20190815060718.3286-1-nishkadg.linux@gmail.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux 2019-08-05T11:00:54+00:00 Neil Armstrong narmstrong@baylibre.com 2019-07-29T12:58:38+00:00 726e8d813771ed9c714d75c9ce58a97b9ddf343d Add the missing pinmux for the pwm_a function on the GPIOE_2 pin. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add the missing pinmux for the pwm_a function on the GPIOE_2 pin.

Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 2019-07-13T22:02:27+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-07-13T22:02:27+00:00 43c95d3694cc448fdf50bd53b7ff3a5bb4655883 Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ... 
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.3 kernel cycle:

  Core changes:

   - Device links can optionally be added between a pin control producer
     and its consumers. This will affect how the system power management
     is handled: a pin controller will not suspend before all of its
     consumers have been suspended.

     This was necessary for the ST Microelectronics STMFX expander and
     need to be tested on other systems as well: it makes sense to make
     this default in the long run.

     Right now it is opt-in per driver.

   - Drive strength can be specified in microamps. With decreases in
     silicon technology, milliamps isn't granular enough, let's make it
     possible to select drive strengths in microamps.

     Right now the Meson (AMlogic) driver needs this.

  New drivers:

   - New subdriver for the Tegra 194 SoC.

   - New subdriver for the Qualcomm SDM845.

   - New subdriver for the Qualcomm SM8150.

   - New subdriver for the Freescale i.MX8MN (Freescale is now a product
     line of NXP).

   - New subdriver for Marvell MV98DX1135.

  Driver improvements:

   - The Bitmain BM1880 driver now supports pin config in addition to
     muxing.

   - The Qualcomm drivers can now reserve some GPIOs as taken aside and
     not usable for users. This is used in ACPI systems to take out some
     GPIO lines used by the BIOS so that noone else (neither kernel nor
     userspace) will play with them by mistake and crash the machine.

   - A slew of refurbishing around the Aspeed drivers (board management
     controllers for servers) in preparation for the new Aspeed AST2600
     SoC.

   - A slew of improvements over the SH PFC drivers as usual.

   - Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: aspeed: Strip moved macros and structs from private header
  pinctrl: aspeed: Fix missed include
  pinctrl: baytrail: Use GENMASK() consistently
  pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
  pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
  pinctrl: qcom: Add SM8150 pinctrl driver
  dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
  dt-bindings: pinctrl: qcom: Document missing gpio nodes
  pinctrl: aspeed: Add implementation-related documentation
  pinctrl: aspeed: Split out pinmux from general pinctrl
  pinctrl: aspeed: Clarify comment about strapping W1C
  pinctrl: aspeed: Correct comment that is no longer true
  MAINTAINERS: Add entry for ASPEED pinctrl drivers
  dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Split bindings document in two
  pinctrl: qcom: Add irq_enable callback for msm gpio
  pinctrl: madera: Fixup SPDX headers
  pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
  pinctrl: tegra: Add bitmask support for parked bits
  ...
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 446 2019-06-05T15:37:18+00:00 Thomas Gleixner tglx@linutronix.de 2019-06-01T08:09:00+00:00 3c910ecbdda4227abd145967774f92b1a3341493 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 30 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation you should have received a
  copy of the gnu general public license along with this program if
  not see http www gnu org licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 30 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190531190115.962665879@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pinctrl: meson: update with SPDX Licence identifier 2019-06-01T17:28:35+00:00 Neil Armstrong narmstrong@baylibre.com 2019-05-20T14:41:04+00:00 e0cdd3a095f9a933ff74e89e5fc625e4c2f3a7f0 Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: add output support in pinconf 2019-05-24T11:49:32+00:00 Jerome Brunet jbrunet@baylibre.com 2019-05-16T15:13:39+00:00 b22a7f85443e579367dfc2d7f4cb6aa863c3a709 Add pinconf support for PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_OUTPUT in the meson pinctrl driver. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add pinconf support for PIN_CONFIG_OUTPUT_ENABLE and PIN_CONFIG_OUTPUT
in the meson pinctrl driver.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: g12a: add DS bank value 2019-05-23T07:24:46+00:00 Guillaume La Roque glaroque@baylibre.com 2019-05-14T08:26:52+00:00 2484ae57c26a9ad04c71bd82e5349ef35f186219 add drive-strength bank regiter and bit value for G12A SoC Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
add drive-strength bank regiter and bit value for G12A SoC

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: add support of drive-strength-microamp 2019-05-23T07:24:46+00:00 Guillaume La Roque glaroque@baylibre.com 2019-05-14T08:26:51+00:00 6ea3e3bbef3705225bb675a8c57af58420c23f81 drive-strength-microamp is a new feature needed for G12A SoC. the default DS setting after boot is usually 500uA and it is not enough for many functions. We need to be able to set the drive strength to reliably enable things like MMC, I2C, etc ... Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
drive-strength-microamp is a new feature needed for G12A SoC.
the default DS setting after boot is usually 500uA and it is not enough for
many functions. We need to be able to set the drive strength to reliably
enable things like MMC, I2C, etc ...

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: Rework enable/disable bias part 2019-05-23T07:24:46+00:00 Guillaume La Roque glaroque@baylibre.com 2019-05-14T08:26:50+00:00 9959d9a747fddfd9e1a37f2e3fc60cbc956aad3a rework bias enable/disable part to prepare drive-strength integration no functional changes Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
rework bias enable/disable part to prepare drive-strength integration
no functional changes

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>