linux-stable.git/drivers/pinctrl/meson, branch linux-4.1.y Linux kernel stable tree pinctrl: meson: meson8b: fix the NAND DQS pins 2017-07-31T17:37:53+00:00 Martin Blumenstingl martin.blumenstingl@googlemail.com 2017-04-01T13:59:21+00:00 94e7b7e5bbe40762a56e7e56bc3f3844c079b687 [ Upstream commit 97ba26b8a9343008504d4e3a87d212bc07b05212 ] The nand_groups table uses different names for the NAND DQS pins than the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0). This prevents using the NAND DQS pins in the devicetree. Fix this by ensuring that the GROUP() definition and the meson8b_cbus_groups use the same name for these pins. Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Sasha Levin <alexander.levin@verizon.com> 
[ Upstream commit 97ba26b8a9343008504d4e3a87d212bc07b05212 ]

The nand_groups table uses different names for the NAND DQS pins than
the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0).
This prevents using the NAND DQS pins in the devicetree.

Fix this by ensuring that the GROUP() definition and the
meson8b_cbus_groups use the same name for these pins.

Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
pinctrl: Fix gpio/pin mapping for Meson8b 2015-05-19T09:40:52+00:00 Carlo Caione carlo@endlessm.com 2015-05-17T15:57:38+00:00 984cffdeaeb7ea5a21f49a89f638d84d62d08992 The num_pins field in the struct meson_domain_data must include also the missing pins in the Meson8b SoC, otherwise the GPIO <-> pin mapping is broken on this platform. Avoid also the dinamic allocation for GPIOs. Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
The num_pins field in the struct meson_domain_data must include also the
missing pins in the Meson8b SoC, otherwise the GPIO <-> pin mapping is
broken on this platform. Avoid also the dinamic allocation for GPIOs.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Add support for Meson8b 2015-04-07T09:44:40+00:00 Carlo Caione carlo@endlessm.com 2015-03-29T10:56:42+00:00 0fefcb6876d0d650ac2255c57051b31c48c1b165 This patch adds support for the AmLogic Meson8b SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This patch adds support for the AmLogic Meson8b SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
documentation: Extend pinctrl docs for Meson8b 2015-04-07T09:42:38+00:00 Carlo Caione carlo@endlessm.com 2015-03-19T21:34:11+00:00 faa246debff1cfc0950f73c778f2db83451aa38b Add the compatible string for Meson8b in Meson pinctrl documentation and add new information for Meson8b in source code comments. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add the compatible string for Meson8b in Meson pinctrl documentation
and add new information for Meson8b in source code comments.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Cleanup Meson8 driver 2015-04-07T09:40:42+00:00 Carlo Caione carlo@endlessm.com 2015-03-19T21:34:10+00:00 0cf6f3c2b5ef0b5b3bb82f02edbeda4751b27763 This patch introduces a new PIN macro and few small modifications to simplify and shorten the Meson pinctrl drivers and cleanup the support file for the AmLogic Meson8 SoC. Signed-off-by: Carlo Caione <carlo@endlessm.com> Acked-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This patch introduces a new PIN macro and few small modifications to
simplify and shorten the Meson pinctrl drivers and cleanup the support
file for the AmLogic Meson8 SoC.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: add driver for Amlogic Meson SoCs 2015-01-26T08:13:00+00:00 Beniamino Galvani b.galvani@gmail.com 2015-01-17T18:15:14+00:00 6ac730951104a437bf828683bcf9ba66336c4fa7 This is a driver for the pinmux and GPIO controller available in Amlogic Meson SoCs. It currently supports only Meson8, however the common code should be generic enough to work also for other SoCs after having defined the proper set of functions and groups. GPIO interrupts are not supported at the moment due to lack of documentation. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>