linux-stable.git/drivers/pinctrl/meson/Kconfig, branch linux-rolling-stable Linux kernel stable tree pinctrl: meson: extend build coverage with COMPILE_TEST=y 2026-01-09T09:31:09+00:00 Bartosz Golaszewski bartosz.golaszewski@oss.qualcomm.com 2026-01-06T08:55:20+00:00 d184b5fef6178e721c8c3d0f65eed63aba419f74 We currently only build these drivers on ARM but there's nothing that should stop us from building it with allmodconfig on other architectures. Extend the build coverage for all meson drivers. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Linus Walleij <linusw@kernel.org> 
We currently only build these drivers on ARM but there's nothing that
should stop us from building it with allmodconfig on other
architectures. Extend the build coverage for all meson drivers.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Linus Walleij <linusw@kernel.org>
pinctrl: meson: Do not enable by default during compile testing 2025-04-15T08:08:42+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2025-04-04T11:57:18+00:00 10dca7cdd431b9fe35f28ea43a7137e2f7aa6d6e Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20250404115719.309999-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Enabling the compile test should not cause automatic enabling of all
drivers.  Restrict the default to ARCH also for individual drivers, even
though their choice is not visible without selecting parent Kconfig
symbol, because otherwise selecting parent would select the child during
compile testing.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20250404115719.309999-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Add driver support for Amlogic SoCs 2025-02-27T23:03:18+00:00 Xianwei Zhao xianwei.zhao@amlogic.com 2025-02-12T05:20:52+00:00 6e9be3abb78c2f6c97a51070004a5165702f0ed9 Add a new pinctrl driver for Amlogic SoCs. All future Amlogic SoCs pinctrl drives use this, such A4, A5, S6, S7 etc. To support new Amlogic SoCs, only need to add the corresponding dts file. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-3-282bc2516804@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add a new pinctrl driver for Amlogic SoCs. All future Amlogic
SoCs pinctrl drives use this, such A4, A5, S6, S7 etc. To support
new Amlogic SoCs, only need to add the corresponding dts file.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-3-282bc2516804@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Add driver support for Amlogic T7 SoCs 2023-09-25T13:49:18+00:00 Huqiang Qin huqiang.qin@amlogic.com 2023-09-22T09:43:41+00:00 9681df024c9af234a9b6c56dfa2af227aee3fa59 Add a new pinctrl driver for Amlogic T7 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/20230922094342.637251-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add a new pinctrl driver for Amlogic T7 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20230922094342.637251-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: Add driver support for Amlogic C3 SoCs 2023-07-23T19:23:27+00:00 Huqiang Qin huqiang.qin@amlogic.com 2023-07-14T12:24:41+00:00 ea90ca106c3fbb35508073bd2439ec04d2ff3fc5 Add a new pinctrl driver for Amlogic C3 SoCs which share the same register layout as the previous Amlogic S4. Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com> Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add a new pinctrl driver for Amlogic C3 SoCs which share
the same register layout as the previous Amlogic S4.

Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: Enable COMPILE_TEST 2022-04-18T13:18:52+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2022-04-01T10:36:01+00:00 6671d0bc17866f71b8ca7ea3fb7e6dfc2a8069d2 Enable COMPILE_TEST for a better test coverage. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> 
Enable COMPILE_TEST for a better test coverage.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
pinctrl: meson: add pinctrl driver support for Meson-S4 Soc 2022-01-30T01:52:45+00:00 Qianggui Song qianggui.song@amlogic.com 2022-01-13T03:10:43+00:00 775214d389c259c77ff2b4de50bdaab5c9bd5db3 Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the same register layout as the previous Meson-A1. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add new pinctrl driver for Amlogic's Meson-S4 SoC which share the
same register layout as the previous Meson-A1.

Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/20220113031044.2665-4-qianggui.song@amlogic.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl/meson: enable building as modules 2020-11-05T13:51:38+00:00 Kevin Hilman khilman@baylibre.com 2020-10-26T18:30:25+00:00 9c65441ec823c7889fc3cd1f00208401cf7044d8 Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules. The default is still built-in, this only adds the option of building as modules. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Enable pinctrl drivers for 64-bit Amlogic SoCs to be built as modules.

The default is still built-in, this only adds the option of building
as modules.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20201026183025.31768-1-khilman@baylibre.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: meson: add pinctrl driver support for Meson-A1 SoC 2019-11-19T14:55:26+00:00 Qianggui Song qianggui.song@amlogic.com 2019-11-15T12:03:48+00:00 dabad1ff856116a14773aa81aa5de0591d6875e9 Meson A1 SoC share the same register layout of pinmux with previous Meson-G12A, however there is difference for gpio and pin config register in A1. The main difference is that registers before A1 are grouped by function while those of A1 are by bank. The new register layout is as below: /* first bank */ /* addr */ - P_PADCTRL_GPIOP_I base + 0x00 << 2 - P_PADCTRL_GPIOP_O base + 0x01 << 2 - P_PADCTRL_GPIOP_OEN base + 0x02 << 2 - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2 - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2 - P_PADCTRL_GPIOP_DS base + 0x05 << 2 /* second bank */ - P_PADCTRL_GPIOB_I base + 0x10 << 2 - P_PADCTRL_GPIOB_O base + 0x11 << 2 - P_PADCTRL_GPIOB_OEN base + 0x12 << 2 - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2 - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2 - P_PADCTRL_GPIOB_DS base + 0x15 << 2 Each bank contains at least 6 registers to be configured, if one bank has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24 ,0x25 according to above register layout. For previous chips, registers are grouped according to their functions while registers of A1 are according to bank.Also note that there is no AO bank any more in A1. Current Meson pinctrl driver can cover such change by using base address of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen make wrong value to reg_ds for Socs that do not support drive-strength like AXG.To make things simple, add an extra dt parser function for a1 and remain the old dt parser function for only reg parsing. Signed-off-by: Qianggui Song <qianggui.song@amlogic.com> Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Meson A1 SoC share the same register layout of pinmux with previous
Meson-G12A, however there is difference for gpio and pin config register
in A1. The main difference is that registers before A1 are grouped by
function while those of A1 are by bank. The new register layout is as
below:

/* first bank */              /* addr */
- P_PADCTRL_GPIOP_I         base + 0x00 << 2
- P_PADCTRL_GPIOP_O         base + 0x01 << 2
- P_PADCTRL_GPIOP_OEN       base + 0x02 << 2
- P_PADCTRL_GPIOP_PULL_EN   base + 0x03 << 2
- P_PADCTRL_GPIOP_PULL_UP   base + 0x04 << 2
- P_PADCTRL_GPIOP_DS        base + 0x05 << 2

/* second bank */
- P_PADCTRL_GPIOB_I         base + 0x10 << 2
- P_PADCTRL_GPIOB_O         base + 0x11 << 2
- P_PADCTRL_GPIOB_OEN       base + 0x12 << 2
- P_PADCTRL_GPIOB_PULL_EN   base + 0x13 << 2
- P_PADCTRL_GPIOB_PULL_UP   base + 0x14 << 2
- P_PADCTRL_GPIOB_DS        base + 0x15 << 2

Each bank contains at least 6 registers to be configured, if one bank
has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included.
Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that
is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24
,0x25 according to above register layout. For previous chips, registers
are grouped according to their functions while registers of A1 are
according to bank.Also note that there is no AO bank any more in A1.

Current Meson pinctrl driver can cover such change by using base address
of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen
make wrong value to reg_ds for Socs that do not support drive-strength
like AXG.To make things simple, add an extra dt parser function for
a1 and remain the old dt parser function for only reg parsing.

Signed-off-by: Qianggui Song <qianggui.song@amlogic.com>
Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21T08:50:46+00:00 Thomas Gleixner tglx@linutronix.de 2019-05-19T12:07:45+00:00 ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1 Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>