linux-stable.git/drivers/pinctrl/intel, branch v5.5.7

pinctrl: tigerlake: Tiger Lake uses _HID enumeration

2020-02-24T07:38:33+00:00

[ Upstream commit cd0a32371db73d0b50536a7ca4f036abddff0d1d ]

Turns out that Tiger Lake GPIO will be enumerated using _HID method where
there is only a single ACPI device and multiple BARs so rework the driver
to support that scheme instead.

Fixes: c9ccf71fc807 ("pinctrl: intel: Add Intel Tiger Lake pin controller support")
Signed-off-by: Mika Westerberg 
Signed-off-by: Andy Shevchenko 
Signed-off-by: Sasha Levin

pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins

2020-02-24T07:38:04+00:00

[ Upstream commit a23680594da7a9e2696dbcf4f023e9273e2fa40b ]

Suspending Goodix touchscreens requires changing the interrupt pin to
output before sending them a power-down command. Followed by wiggling
the interrupt pin to wake the device up, after which it is put back
in input mode.

On Bay Trail devices with a Goodix touchscreen direct-irq mode is used
in combination with listing the pin as a normal GpioIo resource.

This works fine, until the goodix driver gets rmmod-ed and then insmod-ed
again. In this case byt_gpio_disable_free() calls
byt_gpio_clear_triggering() which clears the IRQ flags and after that the
(direct) IRQ no longer triggers.

This commit fixes this by adding a check for the BYT_DIRECT_IRQ_EN flag
to byt_gpio_clear_triggering().

Note that byt_gpio_clear_triggering() only gets called from
byt_gpio_disable_free() for direct-irq enabled pins, as these are excluded
from the irq_valid mask by byt_init_irq_valid_mask().

Signed-off-by: Hans de Goede 
Acked-by: Mika Westerberg 
Reviewed-by: Linus Walleij 
Signed-off-by: Andy Shevchenko 
Signed-off-by: Sasha Levin

pinctrl: baytrail: Allocate IRQ chip dynamic

2020-02-14T21:53:06+00:00

commit 539d8bde72c22d760013bf81436d6bb94eb67aed upstream.

Keeping the IRQ chip definition static shares it with multiple instances
of the GPIO chip in the system. This is bad and now we get this warning
from GPIO library:

"detected irqchip that is shared with multiple gpiochips: please fix the driver."

Hence, move the IRQ chip definition from being driver static into the struct
intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance.

Fixes: 9f573b98ca50 ("pinctrl: baytrail: Update irq chip operations")
Depends-on: ca8a958e2acb ("pinctrl: baytrail: Pass irqchip when adding gpiochip")
Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Greg Kroah-Hartman

pinctrl: sunrisepoint: Add missing Interrupt Status register offset

2020-01-09T11:15:35+00:00

Commit 179e5a6114cc ("pinctrl: intel: Remove default Interrupt Status
offset") removes default interrupt status offset of GPIO controllers,
with previous commits explicitly providing the previously default
offsets. However, the is_offset value in SPTH_COMMUNITY is missing,
preventing related irq from being properly detected and handled.

Fixes: f702e0b93cdb ("pinctrl: sunrisepoint: Provide Interrupt Status register offset")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=205745
Cc: stable@vger.kernel.org
Signed-off-by: Boyan Ding 
Acked-by: Mika Westerberg 
Signed-off-by: Andy Shevchenko

pinctrl: cherryview: Pass irqchip when adding gpiochip

2019-12-09T10:55:53+00:00

We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward conversion.

Acked-by: Mika Westerberg 
Signed-off-by: Hans de Goede 
Signed-off-by: Andy Shevchenko

pinctrl: cherryview: Add GPIO <-> pin mapping ranges via callback

2019-12-09T10:55:53+00:00

When IRQ chip is instantiated via GPIO library flow, the few functions,
in particular the ACPI event registration mechanism, on some of ACPI based
platforms expect that the pin ranges are initialized to that point.

Add GPIO <-> pin mapping ranges via callback in the GPIO library flow.

Acked-by: Mika Westerberg 
Signed-off-by: Hans de Goede 
Signed-off-by: Andy Shevchenko

pinctrl: cherryview: Split out irq hw-init into a separate helper function

2019-12-09T10:55:53+00:00

Split out irq hw-init into a separate chv_gpio_irq_init_hw() function.
This is a preparation patch for passing the irqchip when adding the
gpiochip.

Acked-by: Mika Westerberg 
Signed-off-by: Hans de Goede 
Signed-off-by: Andy Shevchenko

pinctrl: baytrail: Pass irqchip when adding gpiochip

2019-12-09T10:55:53+00:00

We need to convert all old gpio irqchips to pass the irqchip
setup along when adding the gpio_chip. For more info see
drivers/gpio/TODO.

For chained irqchips this is a pretty straight-forward conversion.

Cc: Andy Shevchenko 
Cc: Mika Westerberg 
Cc: Thierry Reding 
Signed-off-by: Linus Walleij 
Signed-off-by: Andy Shevchenko 
Reviewed-by: Mika Westerberg 
Reviewed-by: Hans de Goede 
Tested-by: Hans de Goede

pinctrl: baytrail: Add GPIO <-> pin mapping ranges via callback

2019-12-09T10:55:52+00:00

When IRQ chip is instantiated via GPIO library flow, the few functions,
in particular the ACPI event registration mechanism, on some of ACPI based
platforms expect that the pin ranges are initialized to that point.

Add GPIO <-> pin mapping ranges via callback in the GPIO library flow.

Signed-off-by: Andy Shevchenko 
Reviewed-by: Mika Westerberg 
Reviewed-by: Hans de Goede 
Tested-by: Hans de Goede

pinctrl: baytrail: Update North Community pin list

2019-12-09T10:42:13+00:00

Update North Community pin list to be more clear about pin functions.

Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg