linux-stable.git/drivers/pinctrl/intel, branch v4.8.2

pinctrl: cherryview: Do not mask all interrupts in probe

2016-08-22T13:57:04+00:00

The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC
which can be used directly by the platform/BIOS or drivers. One such wire
is used as SCI (System Control Interrupt) which ACPI depends on to be able
to trigger GPEs (General Purpose Events).

The pinctrl driver itself uses another IRQ resource which is wire OR of all
the 8 (or 16) wires and follows what BIOS has programmed to the IntSel
register of each pin.

Currently the driver masks all interrupts at probe time and this prevents
these direct interrupts from working as expected. The reason for this is
that some early stage prototypes had some pins misconfigured causing lots
of spurious interrupts.

We fix this by leaving the interrupt mask untouched. This allows SCI and
other direct interrupts work properly. What comes to the possible spurious
interrupts we switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).

Reported-by: Yu C Chen 
Reported-by: Anisse Astier 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: merrifield: Add missed header

2016-08-10T13:46:28+00:00

On x86 builds the absense of  makes static analyzer and compiler
unhappy which fails to build the driver.

CHECK   drivers/pinctrl/intel/pinctrl-merrifield.c
drivers/pinctrl/intel/pinctrl-merrifield.c:518:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:570:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:575:9:
  error: undefined identifier 'writel'
drivers/pinctrl/intel/pinctrl-merrifield.c:645:17:
  error: undefined identifier 'readl'
  CC      drivers/pinctrl/intel/pinctrl-merrifield.o
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’:
drivers/pinctrl/intel/pinctrl-merrifield.c:518:10:
  error: implicit declaration of function ‘readl’
  [-Werror=implicit-function-declaration]
  value = readl(bufcfg);
            ^
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’:
drivers/pinctrl/intel/pinctrl-merrifield.c:575:2:
  error: implicit declaration of function ‘writel’
  [-Werror=implicit-function-declaration]
  writel(value, bufcfg);
    ^
cc1: some warnings being treated as errors

Add header to the top of the module.

Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2016-07-29T00:06:51+00:00

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...

pinctrl: intel: Protect set wake flow by spin lock

2016-07-11T09:15:33+00:00

It seems intel_gpio_irq_wake() misses lock protection against I/O flow.
Use spin lock here as well.

Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Add Intel Merrifield pin controller support

2016-06-29T07:59:35+00:00

This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: Mika Westerberg 
Signed-off-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: baytrail: Fix mingled clock pins

2016-06-23T09:05:04+00:00

Fix plt clock 3, 4 and 5 pins, which were not in the proper order.

Signed-off-by: Cristina Ciocan 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Prevent force threading of the interrupt handler

2016-06-18T08:35:47+00:00

The pinctrl-intel needs to use request_irq() instead of chained interrupt
handling because it shares the interrupt with multiple GPIO host
controllers found on Intel CPUs. In -rt all such interrupts are forced to
run in thread context which triggers following warning:

 WARNING: CPU: 0 PID: 530 at kernel/irq/handle.c:151 handle_irq_event_percpu+0x23d/0x240
 irq 348 handler irq_default_primary_handler+0x0/0x10 enabled interrupts
 Modules linked in:
 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257c98 ffffffff812d8494 ffff88007a257ce8
  0000000000000000 ffff88007a257cd8 ffffffff8105e554 000000977a257d90
  ffff88007a37a380 000000000000015c 0000000000000002 0000000000000000
 Call Trace:
  [] dump_stack+0x4f/0x6b
  [] __warn+0xe4/0x100
  [] warn_slowpath_fmt+0x4f/0x60
  [] ? __synchronize_hardirq+0x60/0x60
  [] handle_irq_event_percpu+0x23d/0x240
  [] handle_irq_event+0x62/0x90
  [] handle_edge_irq+0x8f/0x190
  [] generic_handle_irq+0x22/0x30
  [] intel_gpio_irq+0xdc/0x150
  [] irq_forced_thread_fn+0x23/0x70
  [] irq_thread+0x13b/0x1d0
  [] ? __schedule+0x2e4/0x5a0
  [] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [] ? irq_thread+0x1d0/0x1d0
  [] ? wake_threads_waitq+0x30/0x30
  [] kthread+0xd4/0xf0
  [] ? _raw_spin_unlock_irq+0x17/0x40
  [] ret_from_fork+0x22/0x40
  [] ? kthread_worker_fn+0x190/0x190

The handle_irq_event_* functions (and I suppose generic_handle_irq()) is
expected to be called with interrupts disabled and they rightfully complain
here because we run in thread context with interrupts enabled.

Fix this by adding IRQF_NO_THREAD flag when the master interrupt is
requested. This prevents forced threading of the interrupt used by the GPIO
host controllers.

Reported-by: Kim Tatt Chuah 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Use raw_spinlock for locking

2016-06-18T08:35:44+00:00

When running -rt kernel and GPIO interrupt happens we get following

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
 in_atomic(): 1, irqs_disabled(): 0, pid: 530, name: irq/14-INT3452:
 Preemption disabled at:[] handle_edge_irq+0x1b/0x190

 CPU: 0 PID: 530 Comm: irq/14-INT3452: Not tainted 4.6.2-rt5 #1060
  0000000000000000 ffff88007a257d58 ffffffff812d8494 0000000000000000
  ffff88017a330000 ffff88007a257d78 ffffffff81083a11 ffff88007a252430
  ffff88007a252430 ffff88007a257d90 ffffffff8167ef20 000000000000001a
 Call Trace:
  [] dump_stack+0x4f/0x6b
  [] ___might_sleep+0xe1/0x160
  [] rt_spin_lock+0x20/0x50
  [] intel_gpio_irq_ack+0x2d/0x80
  [] handle_edge_irq+0x7b/0x190
  [] generic_handle_irq+0x22/0x30
  [] intel_gpio_irq+0xdc/0x150
  [] irq_forced_thread_fn+0x23/0x70
  [] irq_thread+0x13b/0x1d0
  [] ? __schedule+0x2e4/0x5a0
  [] ? irq_finalize_oneshot.part.37+0xd0/0xd0
  [] ? irq_thread+0x1d0/0x1d0
  [] ? wake_threads_waitq+0x30/0x30
  [] kthread+0xd4/0xf0
  [] ? _raw_spin_unlock_irq+0x17/0x40
  [] ret_from_fork+0x22/0x40
  [] ? kthread_worker_fn+0x190/0x190

The reason why this happens is because intel_gpio_irq_ack() is called with
desc->lock raw_spinlock locked which cannot sleep but our normal spinlock
(which is converted to rtmutex in -rt) is allowed to sleep. This causes
might_sleep() to trigger.

Fix this by converting the normal spinlock to a raw_spinlock.

Reported-by: Kim Tatt Chuah 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl/broxton: enable platform device in the absence of ACPI enumeration

2016-06-15T06:37:42+00:00

This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the Apollo Lake Pinctrl GPIO platform driver.

Signed-off-by: Tan Jui Nee 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: cherryview: add handlers for pin_config_group_get/set

2016-06-15T06:37:40+00:00

Pin config get/set handlers for pin groups were previously not
implemented by this driver.  The pin_config_group_set is
particularly useful for applying a common config setting to all
pins in a specified group with a single call, without the caller
needing to reference each individual pin by name.

Signed-off-by: Dan O'Donovan 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij