linux-stable.git/drivers/pinctrl/intel, branch linux-6.10.y Linux kernel stable tree pinctrl: meteorlake: Add Arrow Lake-H/U ACPI ID 2024-09-18T17:25:18+00:00 Mika Westerberg mika.westerberg@linux.intel.com 2024-06-24T09:55:42+00:00 080c3068715df6e155fc1122534e079ce03ff375 commit a366e46da10d7bfa1a52c3bd31f342a3d0e8e7fe upstream. Intel Arrow Lake-H/U has the same GPIO hardware than Meteor Lake-P but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Cc: stable@vger.kernel.org Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
commit a366e46da10d7bfa1a52c3bd31f342a3d0e8e7fe upstream.

Intel Arrow Lake-H/U has the same GPIO hardware than Meteor Lake-P but
the ACPI ID is different. Add this new ACPI ID to the list of supported
devices.

Cc: stable@vger.kernel.org
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
pinctrl: baytrail: Add pinconf group for uart3 2024-04-08T14:54:48+00:00 Hans de Goede hdegoede@redhat.com 2024-04-07T17:50:49+00:00 5d10a157ebe02ac9b8abacfd529f8b045e8aa41b GPIO_S0_SC57 / GPIO_S0_SC61 can be muxed to PCU_UART_TXD / PCU_UART_RXD, add a pinconf group for this. On Bay Trail board schematics using these pins as UART these are called UART3_TXD / UART3_RXD, name the pinconf group "uart3_grp" to be consistent with the schematics. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
GPIO_S0_SC57 / GPIO_S0_SC61 can be muxed to PCU_UART_TXD / PCU_UART_RXD,
add a pinconf group for this.

On Bay Trail board schematics using these pins as UART these are
called UART3_TXD / UART3_RXD, name the pinconf group "uart3_grp"
to be consistent with the schematics.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
pinctrl: baytrail: Fix selecting gpio pinctrl state 2024-04-08T14:54:48+00:00 Hans de Goede hdegoede@redhat.com 2024-04-07T17:50:48+00:00 fed6d9a8e6a60ecf6506d0ea004040fbaa109927 For all the "score" pin-groups all the intel_pingroup-s to select the non GPIO function are re-used for byt_score_gpio_groups[]. But this is incorrect since a pin-group includes the mode setting, which for the non GPIO functions generally is 1, where as to select the GPIO function mode must be set to 0. So the GPIO function needs separate intel_pingroup-s with their own mode value of 0. Add a new PIN_GROUP_GPIO macro which adds a foo_gpio entry to each pin-group defined this way and update byt_score_gpio_groups[] to point to the new foo_gpio entries. The "sus" usb_oc_grp usb_ulpi_grp and pcu_spi_grp pin-groups are special because these have a non 0 mode value to select the GPIO functions and these already have matching foo_gpio pin-groups, leave these are unchanged. The pmu_clk "sus" groups added in commit 2f46d7f7e959 ("pinctrl: baytrail: Add pinconf group + function for the pmu_clk") do need to use the new PIN_GROUP_GPIO macro. Fixes: 2f46d7f7e959 ("pinctrl: baytrail: Add pinconf group + function for the pmu_clk") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
For all the "score" pin-groups all the intel_pingroup-s to select
the non GPIO function are re-used for byt_score_gpio_groups[].

But this is incorrect since a pin-group includes the mode setting,
which for the non GPIO functions generally is 1, where as to select
the GPIO function mode must be set to 0.

So the GPIO function needs separate intel_pingroup-s with their own mode
value of 0.

Add a new PIN_GROUP_GPIO macro which adds a foo_gpio entry to each
pin-group defined this way and update byt_score_gpio_groups[] to point
to the new foo_gpio entries.

The "sus" usb_oc_grp usb_ulpi_grp and pcu_spi_grp pin-groups are special
because these have a non 0 mode value to select the GPIO functions and
these already have matching foo_gpio pin-groups, leave these are unchanged.

The pmu_clk "sus" groups added in commit 2f46d7f7e959 ("pinctrl: baytrail:
Add pinconf group + function for the pmu_clk") do need to use the new
PIN_GROUP_GPIO macro.

Fixes: 2f46d7f7e959 ("pinctrl: baytrail: Add pinconf group + function for the pmu_clk")
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
pwm: lpss-*: Make use of devm_pwmchip_alloc() function 2024-02-19T10:04:11+00:00 Uwe Kleine-König u.kleine-koenig@pengutronix.de 2024-02-14T09:31:54+00:00 05013062a89fa4c2d5913dfb81a8ae0268e0a9dc This prepares the pwm-lpss drivers to further changes of the pwm core outlined in the commit introducing devm_pwmchip_alloc(). There is no intended semantical change and the driver should behave as before. Reviewed-by: Andy Shevchenko <andy@kernel.org> Link: https://lore.kernel.org/r/b567ab5dd992e361eb884fa6c2cac11be9c7dde3.1707900770.git.u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> 
This prepares the pwm-lpss drivers to further changes of the pwm core
outlined in the commit introducing devm_pwmchip_alloc(). There is no
intended semantical change and the driver should behave as before.

Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/b567ab5dd992e361eb884fa6c2cac11be9c7dde3.1707900770.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Merge tag 'intel-pinctrl-v6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel 2023-12-18T22:42:42+00:00 Linus Walleij linus.walleij@linaro.org 2023-12-18T22:42:42+00:00 7085e4e2ff436df5d65811b39923dae3c218d843 intel-pinctrl for v6.8-1 * New agnostic driver to support Lunar Lake and newer platforms * New driver for Intel Meteor Point-S (PCH for Meteor Lake-S) * Update drivers to use new PM helpers * Use RAII for locking in a few drivers (Raag, Andy) * Reduce locking scope in some functions (Raag) * Miscellaneous cleanups (Raag) The following is an automated git shortlog grouped by driver: alderlake: - Switch to use Intel pin control PM ops baytrail: - Simplify code with cleanup helpers - Move default strength assignment to a switch-case - Factor out byt_gpio_force_input_mode() - Fix types of config value in byt_pin_config_set() broxton: - Switch to use Intel pin control PM ops cannonlake: - Switch to use Intel pin control PM ops cedarfork: - Switch to use Intel pin control PM ops denverton: - Switch to use Intel pin control PM ops elkhartlake: - Switch to use Intel pin control PM ops emmitsburg: - Switch to use Intel pin control PM ops geminilake: - Switch to use Intel pin control PM ops icelake: - Switch to use Intel pin control PM ops intel: - Add Intel Meteor Point pin controller and GPIO support - use the correct _PM_OPS() export macro - Add a generic Intel pin control platform driver - Revert "Unexport intel_pinctrl_probe()" - allow independent COMPILE_TEST - Refactor intel_pinctrl_get_soc_data() - Move default strength assignment to a switch-case - Make PM ops functions static - Provide Intel pin control wide PM ops structure jasperlake: - Switch to use Intel pin control PM ops lakefield: - Switch to use Intel pin control PM ops lewisburg: - Switch to use Intel pin control PM ops lynxpoint: - Simplify code with cleanup helpers meteorlake: - Switch to use Intel pin control PM ops sunrisepoint: - Switch to use Intel pin control PM ops tangier: - simplify locking using cleanup helpers - Move default strength assignment to a switch-case - Enable 910 Ohm bias tigerlake: - Switch to use Intel pin control PM ops Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
intel-pinctrl for v6.8-1

* New agnostic driver to support Lunar Lake and newer platforms
* New driver for Intel Meteor Point-S (PCH for Meteor Lake-S)
* Update drivers to use new PM helpers
* Use RAII for locking in a few drivers (Raag, Andy)
* Reduce locking scope in some functions (Raag)
* Miscellaneous cleanups (Raag)

The following is an automated git shortlog grouped by driver:

alderlake:
 -  Switch to use Intel pin control PM ops

baytrail:
 -  Simplify code with cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Factor out byt_gpio_force_input_mode()
 -  Fix types of config value in byt_pin_config_set()

broxton:
 -  Switch to use Intel pin control PM ops

cannonlake:
 -  Switch to use Intel pin control PM ops

cedarfork:
 -  Switch to use Intel pin control PM ops

denverton:
 -  Switch to use Intel pin control PM ops

elkhartlake:
 -  Switch to use Intel pin control PM ops

emmitsburg:
 -  Switch to use Intel pin control PM ops

geminilake:
 -  Switch to use Intel pin control PM ops

icelake:
 -  Switch to use Intel pin control PM ops

intel:
 -  Add Intel Meteor Point pin controller and GPIO support
 -  use the correct _PM_OPS() export macro
 -  Add a generic Intel pin control platform driver
 -  Revert "Unexport intel_pinctrl_probe()"
 -  allow independent COMPILE_TEST
 -  Refactor intel_pinctrl_get_soc_data()
 -  Move default strength assignment to a switch-case
 -  Make PM ops functions static
 -  Provide Intel pin control wide PM ops structure

jasperlake:
 -  Switch to use Intel pin control PM ops

lakefield:
 -  Switch to use Intel pin control PM ops

lewisburg:
 -  Switch to use Intel pin control PM ops

lynxpoint:
 -  Simplify code with cleanup helpers

meteorlake:
 -  Switch to use Intel pin control PM ops

sunrisepoint:
 -  Switch to use Intel pin control PM ops

tangier:
 -  simplify locking using cleanup helpers
 -  Move default strength assignment to a switch-case
 -  Enable 910 Ohm bias

tigerlake:
 -  Switch to use Intel pin control PM ops

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: intel: Add Intel Meteor Point pin controller and GPIO support 2023-12-15T15:09:36+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2023-12-14T15:46:53+00:00 ebe7f3393784857c487bf82f86813a8b1384e278 This driver supports pinctrl/GPIO hardware found on Intel Meteor Point (a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces including GPIO interrupts. Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
This driver supports pinctrl/GPIO hardware found on Intel Meteor Point
(a Meteor Lake PCH) providing users a pinctrl and GPIO interfaces
including GPIO interrupts.

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
pinctrl: baytrail: use gpiochip_dup_line_label() 2023-12-08T08:26:35+00:00 Bartosz Golaszewski bartosz.golaszewski@linaro.org 2023-12-04T09:35:06+00:00 c73505c8a001f8ce63b8ad92c9cd0176fe3c22a4 Use the new gpiochip_dup_line_label() helper to safely retrieve the descriptor label. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> 
Use the new gpiochip_dup_line_label() helper to safely retrieve the
descriptor label.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
pinctrl: baytrail: Simplify code with cleanup helpers 2023-11-24T12:33:30+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2023-11-22T17:50:39+00:00 6191e49de389f57a2d34fdfe2c5df7fca2a1f246 Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> 
Use macros defined in linux/cleanup.h to automate resource lifetime
control in the driver.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
pinctrl: baytrail: Move default strength assignment to a switch-case 2023-11-24T12:33:30+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2023-11-22T17:50:38+00:00 078d83033a76ddbb030e87ed2a56eb28a57a7b34 When ->pin_config_set() is called from the GPIO library (assumed GpioIo() ACPI resource), the argument can be 1, when, for example, PullDefault is provided. In such case we supply sane default in the driver. Move that default assingment to a switch-case, so it will be consolidated in one place. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> 
When ->pin_config_set() is called from the GPIO library (assumed
GpioIo() ACPI resource), the argument can be 1, when, for example,
PullDefault is provided. In such case we supply sane default in
the driver. Move that default assingment to a switch-case, so
it will be consolidated in one place.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
pinctrl: baytrail: Factor out byt_gpio_force_input_mode() 2023-11-24T12:33:30+00:00 Andy Shevchenko andriy.shevchenko@linux.intel.com 2023-11-22T17:50:37+00:00 5398a0e23cf82e2a69088d7080bc588bc07f4284 There is a piece of code that it being used at least twice. Factor it out. Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> 
There is a piece of code that it being used at least twice.
Factor it out.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>