linux-stable.git/drivers/pinctrl/intel, branch linux-4.8.y

pinctrl: cherryview: Prevent possible interrupt storm on resume

2016-11-18T09:51:46+00:00

commit d2cdf5dc58f6970e9d9d26e47974c21fe87983f3 upstream.

When the system is suspended to S3 the BIOS might re-initialize certain
GPIO pins back to their original state or it may re-program interrupt mask
of others. For example Acer TravelMate B116-M had BIOS bug where certain
GPIO pin (MF_ISH_GPIO_5) was programmed to trigger on high level, and the
pin state was high once the BIOS gave control to the OS on resume.

This triggers lots of messages like:

 irq 117, desc: ffff88017a61e600, depth: 1, count: 0, unhandled: 0
 ->handle_irq():  ffffffff8109b613, handle_bad_irq+0x0/0x1e0
 ->irq_data.chip(): ffffffffa0020180, chv_pinctrl_exit+0x2d84/0x12 [pinctrl_cherryview]
 ->action():           (null)
    IRQ_NOPROBE set

We reset the mask back to known state in chv_pinctrl_resume() but that is
called only after device interrupts have already been enabled.

Now, this particular issue was fixed by upgrading the BIOS to the latest
(v1.23) but not everybody upgrades their BIOSes so we fix it up in the
driver as well.

Prevent the possible interrupt storm by moving suspend and resume hooks to
be called at _noirq time instead. Since device interrupts are still
disabled we can restore the mask back to known state before interrupt storm
happens.

Reported-by: Christian Steiner 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: cherryview: Serialize register access in suspend/resume

2016-11-18T09:51:45+00:00

commit 56211121c0825cd188caad05574fdc518d5cac6f upstream.

If async suspend is enabled, the driver may access registers concurrently
with another instance which may fail because of the bug in Cherryview GPIO
hardware. Prevent this by taking the shared lock while accessing the
hardware in suspend and resume hooks.

Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: baytrail: Fix lockdep

2016-10-28T07:45:28+00:00

commit a171bc51fa697021e1b2082d7e95c12a363bc0a9 upstream.

Initialize the spinlock before using it.

INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.8.0-dwc-bisect #4
Hardware name: Intel Corp. VALLEYVIEW C0 PLATFORM/BYT-T FFD8, BIOS BLAKFF81.X64.0088.R10.1403240443 FFD8_X64_R_2014_13_1_00 03/24/2014
 0000000000000000 ffff8800788ff770 ffffffff8133d597 0000000000000000
 0000000000000000 ffff8800788ff7e0 ffffffff810cfb9e 0000000000000002
 ffff8800788ff7d0 ffffffff8205b600 0000000000000002 ffff8800788ff7f0
Call Trace:
 [] dump_stack+0x67/0x90
 [] register_lock_class+0x52e/0x540
 [] __lock_acquire+0x81/0x16b0
 [] ? save_trace+0x41/0xd0
 [] ? __lock_acquire+0x13b2/0x16b0
 [] ? __lock_is_held+0x4a/0x70
 [] lock_acquire+0xba/0x220
 [] ? byt_gpio_get_direction+0x3e/0x80
 [] _raw_spin_lock_irqsave+0x47/0x60
 [] ? byt_gpio_get_direction+0x3e/0x80
 [] byt_gpio_get_direction+0x3e/0x80
 [] gpiochip_add_data+0x319/0x7d0
 [] ? _raw_spin_unlock_irqrestore+0x43/0x70
 [] byt_pinctrl_probe+0x2fb/0x620
 [] platform_drv_probe+0x3c/0xa0
...

Based on the diff it looks like the problem was introduced in
commit 71e6ca61e826 ("pinctrl: baytrail: Register pin control handling")
but I wasn't able to verify that empirically as the parent commit
just oopsed when I tried to boot it.

Cc: Cristina Ciocan 
Fixes: 71e6ca61e826 ("pinctrl: baytrail: Register pin control handling")
Signed-off-by: Ville Syrjälä 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: intel: Only restore pins that are used by the driver

2016-10-28T07:45:28+00:00

commit c538b9436751a0be2e1246b48353bc23156bdbcc upstream.

Dell XPS 13 (and maybe some others) uses a GPIO (CPU_GP_1) during suspend
to explicitly disable USB touchscreen interrupt. This is done to prevent
situation where the lid is closed the touchscreen is left functional.

The pinctrl driver (wrongly) assumes it owns all pins which are owned by
host and not locked down. It is perfectly fine for BIOS to use those pins
as it is also considered as host in this context.

What happens is that when the lid of Dell XPS 13 is closed, the BIOS
configures CPU_GP_1 low disabling the touchscreen interrupt. During resume
we restore all host owned pins to the known state which includes CPU_GP_1
and this overwrites what the BIOS has programmed there causing the
touchscreen to fail as no interrupts are reaching the CPU anymore.

Fix this by restoring only those pins we know are explicitly requested by
the kernel one way or other.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=176361
Reported-by: AceLan Kao 
Tested-by: AceLan Kao 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: cherryview: Do not mask all interrupts in probe

2016-08-22T13:57:04+00:00

The Cherryview GPIO controller has 8 or 16 wires connected to the I/O-APIC
which can be used directly by the platform/BIOS or drivers. One such wire
is used as SCI (System Control Interrupt) which ACPI depends on to be able
to trigger GPEs (General Purpose Events).

The pinctrl driver itself uses another IRQ resource which is wire OR of all
the 8 (or 16) wires and follows what BIOS has programmed to the IntSel
register of each pin.

Currently the driver masks all interrupts at probe time and this prevents
these direct interrupts from working as expected. The reason for this is
that some early stage prototypes had some pins misconfigured causing lots
of spurious interrupts.

We fix this by leaving the interrupt mask untouched. This allows SCI and
other direct interrupts work properly. What comes to the possible spurious
interrupts we switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).

Reported-by: Yu C Chen 
Reported-by: Anisse Astier 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: merrifield: Add missed header

2016-08-10T13:46:28+00:00

On x86 builds the absense of  makes static analyzer and compiler
unhappy which fails to build the driver.

CHECK   drivers/pinctrl/intel/pinctrl-merrifield.c
drivers/pinctrl/intel/pinctrl-merrifield.c:518:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:570:17:
  error: undefined identifier 'readl'
drivers/pinctrl/intel/pinctrl-merrifield.c:575:9:
  error: undefined identifier 'writel'
drivers/pinctrl/intel/pinctrl-merrifield.c:645:17:
  error: undefined identifier 'readl'
  CC      drivers/pinctrl/intel/pinctrl-merrifield.o
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_pin_dbg_show’:
drivers/pinctrl/intel/pinctrl-merrifield.c:518:10:
  error: implicit declaration of function ‘readl’
  [-Werror=implicit-function-declaration]
  value = readl(bufcfg);
            ^
drivers/pinctrl/intel/pinctrl-merrifield.c: In function ‘mrfld_update_bufcfg’:
drivers/pinctrl/intel/pinctrl-merrifield.c:575:2:
  error: implicit declaration of function ‘writel’
  [-Werror=implicit-function-declaration]
  writel(value, bufcfg);
    ^
cc1: some warnings being treated as errors

Add header to the top of the module.

Fixes: 4e80c8f50574 ("pinctrl: intel: Add Intel Merrifield pin controller support")
Signed-off-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2016-07-29T00:06:51+00:00

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v4.8 kernel cycle.

  Nothing stands out as especially exiting: new drivers, new subdrivers,
  lots of cleanups and incremental features.

  Business as usual.

  New drivers:

   - New driver for Oxnas pin control and GPIO.  This ARM-based chipset
     is used in a few storage (NAS) type devices.

   - New driver for the MAX77620/MAX20024 pin controller portions.

   - New driver for the Intel Merrifield pin controller.

  New subdrivers:

   - New subdriver for the Qualcomm MDM9615

   - New subdriver for the STM32F746 MCU

   - New subdriver for the Broadcom NSP SoC.

  Cleanups:

   - Demodularization of bool compiled-in drivers.

  Apart from this there is just regular incremental improvements to a
  lot of drivers, especially Uniphier and PFC"

* tag 'pinctrl-v4.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (131 commits)
  pinctrl: fix pincontrol definition for marvell
  pinctrl: xway: fix typo
  Revert "pinctrl: amd: make it explicitly non-modular"
  pinctrl: iproc: Add NSP and Stingray GPIO support
  pinctrl: Update iProc GPIO DT bindings
  pinctrl: bcm: add OF dependencies
  pinctrl: ns2: remove redundant dev_err call in ns2_pinmux_probe()
  pinctrl: Add STM32F746 MCU support
  pinctrl: intel: Protect set wake flow by spin lock
  pinctrl: nsp: remove redundant dev_err call in nsp_pinmux_probe()
  pinctrl: uniphier: add Ethernet pin-mux settings
  sh-pfc: Use PTR_ERR_OR_ZERO() to simplify the code
  pinctrl: ns2: fix return value check in ns2_pinmux_probe()
  pinctrl: qcom: update DT bindings with ebi2 groups
  pinctrl: qcom: establish proper EBI2 pin groups
  pinctrl: imx21: Remove the MODULE_DEVICE_TABLE() macro
  Documentation: dt: Add new compatible to STM32 pinctrl driver bindings
  includes: dt-bindings: Add STM32F746 pinctrl DT bindings
  pinctrl: sunxi: fix nand0 function name for sun8i
  pinctrl: uniphier: remove pointless pin-mux settings for PH1-LD11
  ...

pinctrl: intel: Protect set wake flow by spin lock

2016-07-11T09:15:33+00:00

It seems intel_gpio_irq_wake() misses lock protection against I/O flow.
Use spin lock here as well.

Signed-off-by: Andy Shevchenko 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij

pinctrl: intel: Add Intel Merrifield pin controller support

2016-06-29T07:59:35+00:00

This driver adds pinctrl support for Intel Merrifield. The IP block which is
called Family-Level Interface Shim is a separate entity in SoC. The GPIO driver
(gpio-intel-mid.c) will be updated accordingly to support pinctrl interface.

Reviewed-by: Mika Westerberg 
Signed-off-by: Andy Shevchenko 
Signed-off-by: Linus Walleij

pinctrl: baytrail: Fix mingled clock pins

2016-06-23T09:05:04+00:00

Fix plt clock 3, 4 and 5 pins, which were not in the proper order.

Signed-off-by: Cristina Ciocan 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij