linux-stable.git/drivers/pinctrl/aspeed, branch v4.13.2

pinctrl: aspeed: g5: Add pinconf support

2017-04-24T12:55:50+00:00

Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system,
using the strategy outlined in the commit message for the change to the
Aspeed pinctrl core.

Signed-off-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: g4: Add pinconf support

2017-04-24T12:55:03+00:00

Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto
system, using the strategy outlined in the commit message for the
change to the Aspeed pinctrl core.

Signed-off-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: Add core pinconf support

2017-04-24T12:53:58+00:00

Several pinconf parameters have a fairly straight-forward mapping onto
the Aspeed pin controller. These include management of pull-down bias,
drive-strength, and some debounce configuration.

Pin biasing largely is managed on a per-GPIO-bank basis, aside from the
ADC and RMII/RGMII pins. As the bias configuration for each pin in a
bank maps onto a single per-bank bit, configuration tables will be
introduced to describe the ranges of pins and the supported pinconf
parameter. The use of tables also helps with the sparse support of
pinconf properties, and the fact that not all GPIO banks support
biasing or drive-strength configuration.

Further, as the pin controller uses a consistent approach for bias and
drive strength configuration at the register level, a second table is
defined for looking up the the bit-state required to enable or query the
provided configuration.

Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto
system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU.
The test method was to set the appropriate bits via devmem and verify
the result through the controller's pinconf-pins debugfs file. This
simultaneously validates the get() path and half of the set() path. The
remainder of the set() path was validated by configuring a handful of
pins via the devicetree with the supported pinconf properties and
verifying the appropriate registers were touched.

Signed-off-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: Fix unused-const-variable warnings

2017-04-11T07:47:44+00:00

Three video input signals suffered from a search/replace failure in
some copied code.

Signed-off-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: Allow disabling Port D and Port E loopback mode

2017-03-14T13:42:22+00:00

Port D and port E GPIO loopback modes are commonly enabled via hardware
straps for use with front-panel buttons.  When the BMC is powered
off or fails to boot, the front-panel buttons are directly connected to
the host chipset via the loopback to allow direct power-on and reset
control. Once the BMC has booted, the loopback mode must be disabled for
the BMC to take over control of host power-on and reset.

Disabling these loopback modes requires writing to the hardware strap
register which violates the current design of assuming the system
designer chose the strap settings for a specific reason and they should
be treated as read-only. Only the two bits of the strap register related
to these loopback modes are allowed to be written and comments have been
added to explain why.

Signed-off-by: Rick Altherr 
Acked-by: Joel Stanley 
Reviewed-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: g4: Fix mux configuration for GPIOs AA[4-7], AB[0-7]

2017-01-26T13:42:39+00:00

Incorrect video output configuration bits were being tested on pins in
GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16}
functions are the highest priority for the relevant pins and also the
default function, so we require the relevant video output configuration
be disabled to mux GPIO functionality. As the wrong bits were being
tested a GPIO export would succeed but leave the pin in an unresponsive
state (i.e. value updates were ignored).

This misbehaviour was discovered as part of extending the GPIO
controller's support to cover banks Y, Z, AA, AB and AC (AC in the case
of the g5 SoC).

Fixes: 6d329f14a75f ("pinctrl: aspeed-g4: Add mux configuration for all pins")
Signed-off-by: Andrew Jeffery 
Signed-off-by: Linus Walleij

pinctrl: aspeed: Fix kerneldoc return descriptions

2016-12-28T00:23:10+00:00

Signed-off-by: Andrew Jeffery 
Acked-by: Joel Stanley 
Signed-off-by: Linus Walleij

pinctrl: aspeed-g5: Add mux configuration for all pins

2016-12-28T00:21:23+00:00

The patch introducing the g5 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms and the AST2500 evaluation board.
Now, update the bindings document to reflect the complete functionality
and implement the necessary pin configuration tables in the driver.

Signed-off-by: Andrew Jeffery 
Acked-by: Joel Stanley 
Acked-by: Rob Herring 
Signed-off-by: Linus Walleij

pinctrl: aspeed-g4: Add mux configuration for all pins

2016-12-27T22:17:23+00:00

The patch introducing the g4 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms. Now, update the bindings document
to reflect the complete functionality and implement the necessary pin
configuration tables in the driver.

Cc: Timothy Pearson 
Signed-off-by: Andrew Jeffery 
Acked-by: Joel Stanley 
Acked-by: Rob Herring 
Signed-off-by: Linus Walleij

pinctrl: aspeed: Read and write bits in LPC and GFX controllers

2016-12-27T22:15:32+00:00

The System Control Unit IP block in the Aspeed SoCs is typically where
the pinmux configuration is found, but not always. A number of pins
depend on state in one of LPC Host Control (LHC) or SoC Display
Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
means to adjust these as necessary.

We use syscon to cast a regmap over the GFX and LPC blocks, which is
used as an arbitration layer between the relevant driver and the pinctrl
subsystem. The regmaps are then exposed to the SoC-specific pinctrl
drivers by phandles in the devicetree, and are selected during a mux
request by querying a new 'ip' member in struct aspeed_sig_desc.

Signed-off-by: Andrew Jeffery 
Reviewed-by: Joel Stanley 
Acked-by: Rob Herring 
Signed-off-by: Linus Walleij