linux-stable.git/drivers/pinctrl/Makefile, branch linux-5.17.y

pinctrl: Place correctly CONFIG_PINCTRL_ST in the Makefile

2022-01-24T14:30:13+00:00

Keep Makefile entries ordered in the same way as Kconfig ones.

Reported-by: Linus Torvalds 
Signed-off-by: Andy Shevchenko

Merge tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2022-01-12T18:56:08+00:00

Pull pin control bulk updates from Linus Walleij:
"Core changes:

- New standard enumerator and corresponding device tree bindings for
output impedance pin configuration. (Implemented and used in the
Renesas rzg2l driver.)

- Cleanup of Kconfig and Makefile to be somewhat orderly and
alphabetic.

New drivers:

- Samsung Exynos 7885 pin controller.

- Ocelot LAN966x pin controller.

- Qualcomm SDX65 pin controller.

- Qualcomm SM8450 pin controller.

- Qualcomm PM8019, PM8226 and PM2250 pin controllers.

- NXP/Freescale i.MXRT1050 pin controller.

- Intel Thunder Bay pin controller.

Enhancements:

- Introduction of the string library helper function
"kasprintf_strarray()" and subsequent use in Rockchip, ST and
Armada pin control drivers, as well as the GPIO mockup driver.

- The Ocelot pin controller has been extensively rewritten to use
regmap and other modern kernel infrastructure.

- The Microchip SGPIO driver has been converted to use regmap.

- The SPEAr driver had been converted to use regmap.

- Substantial cleanups and janitorial on the Apple pin control driver
that was merged for v5.16.

- Janitorial to remove of_node assignments in the GPIO portions that
anyway get this handled in the GPIO core.

- Minor cleanups and improvements in several pin controllers"

* tag 'pinctrl-v5.17-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (98 commits)
pinctrl: imx: fix assigning groups names
dt-bindings: pinctrl: mt8195: add wrapping node of pin configurations
pinctrl: bcm: ns: use generic groups & functions helpers
pinctrl: imx: fix allocation result check
pinctrl: samsung: Use platform_get_irq_optional() to get the interrupt
pinctrl: Propagate firmware node from a parent device
dt-bindings: pinctrl: qcom: Add SDX65 pinctrl bindings
pinctrl: add one more "const" for generic function groups
pinctrl: keembay: rework loops looking for groups names
pinctrl: keembay: comment process of building functions a bit
pinctrl: imx: prepare for making "group_names" in "function_desc" const
ARM: dts: gpio-ranges property is now required
pinctrl: aspeed: fix unmet dependencies on MFD_SYSCON for PINCTRL_ASPEED
pinctrl: Get rid of duplicate of_node assignment in the drivers
pinctrl-sunxi: don't call pinctrl_gpio_direction()
pinctrl-bcm2835: don't call pinctrl_gpio_direction()
pinctrl: bcm2835: Silence uninit warning
pinctrl: Sort Kconfig and Makefile entries alphabetically
pinctrl: Add Intel Thunder Bay pinctrl driver
dt-bindings: pinctrl: Add bindings for Intel Thunderbay pinctrl driver
...

pinctrl: starfive: Add pinctrl driver for StarFive SoCs

2021-12-16T16:24:23+00:00

Add a combined pinctrl and GPIO driver for the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC, which
is said to feature only minor changes to these pinctrl/GPIO parts.

For each "GPIO" there are two registers for configuring the output and
output enable signals which may come from other peripherals. Among these
are two special signals that are constant 0 and constant 1 respectively.
Controlling the GPIOs from software is done by choosing one of these
signals. In other words the same registers are used for both pin muxing
and controlling the GPIOs, which makes it easier to combine the pinctrl
and GPIO driver in one.

I wrote the pinconf and pinmux parts, but the GPIO part of the code is
based on the GPIO driver in the vendor tree written by Huan Feng with
cleanups and fixes by Drew and me.

Datasheet: https://github.com/starfive-tech/JH7100_Docs/blob/main/JH7100%20Data%20Sheet%20V01.01.04-EN%20(4-21-2021).pdf
Reviewed-by: Andy Shevchenko 
Reviewed-by: Linus Walleij 
Co-developed-by: Huan Feng 
Signed-off-by: Huan Feng 
Co-developed-by: Drew Fustini 
Signed-off-by: Drew Fustini 
Signed-off-by: Emil Renner Berthing

pinctrl: Sort Kconfig and Makefile entries alphabetically

2021-12-09T13:49:39+00:00

Sort Kconfig and Makefile entries alphabetically for better maintenance
in the future.

While at it fix some style issues, such as:
  - "Say Y"/"Say yes"/"Say Yes" --> "Say Y"
  - "pullup/pulldown" --> "pull-up and pull-down"
  - wrong indentation

Signed-off-by: Andy Shevchenko 
Link: https://lore.kernel.org/r/20211209113456.33977-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij

pinctrl: Add Intel Thunder Bay pinctrl driver

2021-12-09T02:17:39+00:00

About Intel Thunder Bay:
-----------------------
Intel Thunder Bay is a computer vision AI accelerator SoC based on ARM CPU.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Thunder Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Thunder Bay
SoC.

Co-developed-by: Kiran Kumar S 
Signed-off-by: Kiran Kumar S 
Signed-off-by: Lakshmi Sowjanya D 
Link: https://lore.kernel.org/r/20211201072626.19599-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij

pinctrl: add pinctrl/GPIO driver for Apple SoCs

2021-10-26T22:16:52+00:00

This driver adds support for the pinctrl / GPIO hardware found
on some Apple SoCs.

Co-developed-by: Stan Skowronek 
Signed-off-by: Stan Skowronek 
Signed-off-by: Joey Gouly 
Acked-by: Hector Martin 
Reviewed-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20211026175815.52703-5-joey.gouly@arm.com
Signed-off-by: Linus Walleij

pinctrl: Add Intel Keem Bay pinctrl driver

2021-08-11T13:13:14+00:00

About Intel Keem Bay:
-------------------
Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU.
Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst.

Pinctrl IP:
----------
The SoC has a customised pinmux controller IP which controls pin
multiplexing and configuration.

Keem Bay pinctrl IP is not based on and have nothing in common with the
existing pinctrl drivers. The registers used are incompatible with the
existing drivers, so it requires a new driver.

Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC.

Co-developed-by: Vineetha G. Jaya Kumaran 
Signed-off-by: Vineetha G. Jaya Kumaran 
Co-developed-by: Vijayakannan Ayyathurai 
Signed-off-by: Vijayakannan Ayyathurai 
Signed-off-by: Lakshmi Sowjanya D 
Reviewed-by: Mark Gross 
Reviewed-by: Linus Walleij 
Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com
Signed-off-by: Linus Walleij

pinctrl: Add Xilinx ZynqMP pinctrl driver support

2021-04-22T09:13:04+00:00

Adding pinctrl driver for Xilinx ZynqMP platform.
This driver queries pin information from firmware and registers
pin control accordingly.

Signed-off-by: Sai Krishna Potthuri 
Link: https://lore.kernel.org/r/1619080202-31924-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com
Signed-off-by: Linus Walleij

Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2021-02-26T18:28:35+00:00

Pull RISC-V updates from Palmer Dabbelt:
"A handful of new RISC-V related patches for this merge window:

- A check to ensure drivers are properly using uaccess. This isn't
manifesting with any of the drivers I'm currently using, but may
catch errors in new drivers.

- Some preliminary support for the FU740, along with the HiFive
Unleashed it will appear on.

- NUMA support for RISC-V, which involves making the arm64 code
generic.

- Support for kasan on the vmalloc region.

- A handful of new drivers for the Kendryte K210, along with the DT
plumbing required to boot on a handful of K210-based boards.

- Support for allocating ASIDs.

- Preliminary support for kernels larger than 128MiB.

- Various other improvements to our KASAN support, including the
utilization of huge pages when allocating the KASAN regions.

We may have already found a bug with the KASAN_VMALLOC code, but it's
passing my tests. There's a fix in the works, but that will probably
miss the merge window.

* tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits)
riscv: Improve kasan population by using hugepages when possible
riscv: Improve kasan population function
riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
riscv: Improve kasan definitions
riscv: Get rid of MAX_EARLY_MAPPING_SIZE
soc: canaan: Sort the Makefile alphabetically
riscv: Disable KSAN_SANITIZE for vDSO
riscv: Remove unnecessary declaration
riscv: Add Canaan Kendryte K210 SD card defconfig
riscv: Update Canaan Kendryte K210 defconfig
riscv: Add Kendryte KD233 board device tree
riscv: Add SiPeed MAIXDUINO board device tree
riscv: Add SiPeed MAIX GO board device tree
riscv: Add SiPeed MAIX DOCK board device tree
riscv: Add SiPeed MAIX BiT board device tree
riscv: Update Canaan Kendryte K210 device tree
dt-bindings: add resets property to dw-apb-timer
dt-bindings: fix sifive gpio properties
dt-bindings: update sifive uart compatible string
dt-bindings: update sifive clint compatible string
...

pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver

2021-02-19T07:18:01+00:00

Add the pinctrl-k210.c pinctrl driver for the Canaan Kendryte K210
field programmable IO array (FPIOA) to allow configuring the SoC pin
functions. The K210 has 48 programmable pins which can take any of 256
possible functions.

This patch is inspired from the k210 pinctrl driver for the u-boot
project and contains many direct contributions from Sean Anderson.

The MAINTAINERS file is updated, adding the entry "CANAAN/KENDRYTE K210
SOC FPIOA DRIVER" with myself listed as maintainer for this driver.

Cc: Linus Walleij 
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Sean Anderson 
Signed-off-by: Damien Le Moal 
Reviewed-by: Linus Walleij 
Signed-off-by: Palmer Dabbelt