linux-stable.git/drivers/phy, branch v6.6.3

phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs

2023-11-28T17:19:45+00:00

[ Upstream commit 99a517a582fc1272d1d3cf3b9e671a14d7db77b8 ]

The vendor kernel zeroes out all tuning data outside the init sequence
as part of initialization. Follow suit to avoid UB.

Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-3-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields

2023-11-28T17:19:45+00:00

[ Upstream commit 4ba2e52718c0ce4ece6a269bec84319c355c030f ]

Switch to regmap_fields, so that the values written into registers are
sanitized by their explicit sizes and the different registers are
structured in an iterable object to make external changes to the init
sequence simpler.

Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230830-topic-eusb2_override-v2-2-7d8c893d93f6@linaro.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

Merge tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2023-10-22T17:11:10+00:00

Pull phy fixes from Vinod Koul:

 - mapphone-mdm6600 runtime pm & pinctrl handling fixes

 - Qualcomm qmp usb pcs register fixes, qmp pcie register size warning
   fix, m31 fixes for wrong pointer in PTR_ERR and dropping wrong vreg
   check, qmp combo fix for 8550 power config register

 - realtek usb fix for debugfs_create_dir() and kconfig dependency

* tag 'phy-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy:
  phy: realtek: Realtek PHYs should depend on ARCH_REALTEK
  phy: qualcomm: Fix typos in comments
  phy: qcom-qmp-combo: initialize PCS_USB registers
  phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1
  phy: qcom: m31: Remove unwanted qphy->vreg is NULL check
  phy: realtek: usb: Drop unnecessary error check for debugfs_create_dir()
  phy: qcom: phy-qcom-m31: change m31_ipq5332_regs to static
  phy: qcom: phy-qcom-m31: fix wrong pointer pass to PTR_ERR()
  dt-bindings: phy: qcom,ipq8074-qmp-pcie: fix warning regarding reg size
  phy: qcom-qmp-usb: split PCS_USB init table for sc8280xp and sa8775p
  phy: qcom-qmp-usb: initialize PCS_USB registers
  phy: mapphone-mdm6600: Fix pinctrl_pm handling for sleep pins
  phy: mapphone-mdm6600: Fix runtime PM for remove
  phy: mapphone-mdm6600: Fix runtime disable on probe

phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers

2023-10-06T09:59:52+00:00

The protocol converter configuration registers PCC8, PCCC, PCCD
(implemented by the driver), as well as others, control protocol
converters from multiple lanes (each represented as a different
struct phy). So, if there are simultaneous calls to phy_set_mode_ext()
to lanes sharing the same PCC register (either for the "old" or for the
"new" protocol), corruption of the values programmed to hardware is
possible, because lynx_28g_rmw() has no locking.

Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take
the global spinlock from the phy_ops :: set_mode() implementation. There
are no other callers which modify PCC registers.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

phy: lynx-28g: lock PHY while performing CDR lock workaround

2023-10-06T09:59:52+00:00

lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset
the lane receiver if the CDR has not locked onto bit transitions in the
RX stream. But the PHY consumer may do stuff with the PHY simultaneously,
and that isn't okay. Block concurrent generic PHY calls by holding the
PHY mutex from this workqueue.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

phy: lynx-28g: cancel the CDR check work item on the remove path

2023-10-06T09:59:52+00:00

The blamed commit added the CDR check work item but didn't cancel it on
the remove path. Fix this by adding a remove function which takes care
of it.

Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Ioana Ciornei 
Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

phy: realtek: Realtek PHYs should depend on ARCH_REALTEK

2023-09-29T16:17:37+00:00

The Realtek SoC USB2 and USB3 PHY Transceivers are only present on
Realtek Digital Home Center (DHC) RTD series SoCs.  Hence add a
dependency on ARCH_REALTEK, to prevent asking the user about these
drivers when configuring a kernel without Realtek SoC support.

Signed-off-by: Geert Uytterhoeven 
Link: https://lore.kernel.org/r/2892527cac9af6fa8f5e7b8daeffd7d4351fde68.1692113167.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul

phy: qualcomm: Fix typos in comments

2023-09-21T14:24:00+00:00

Fix typo in the description of the 'succesfully'.

Signed-off-by: Bo Liu 
Reviewed-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230912114646.8452-1-liubo03@inspur.com
Signed-off-by: Vinod Koul

phy: qcom-qmp-combo: initialize PCS_USB registers

2023-09-21T14:23:13+00:00

Currently, PCS_USB registers that have their initialization data in a
pcs_usb_tbl table are never initialized. Fix that.

Fixes: fc64623637da ("phy: qcom-qmp-combo,usb: add support for separate PCS_USB region")
Reported-by: Adrien Thierry 
Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-2-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul

phy: qcom-qmp-combo: Square out 8550 POWER_STATE_CONFIG1

2023-09-21T14:23:13+00:00

There are two instances of the POWER_STATE_CONFIG1 register: one in
the PCS space and another one in PCS_USB.

The downstream init sequence pokes the latter one while we've been poking
the former one (and misnamed it as the latter one, impostor!). Fix that
up to avoid UB.

Fixes: 49742e9edab3 ("phy: qcom-qmp-combo: Add support for SM8550")
Reviewed-by: Abel Vesa 
Reviewed-by: Dmitry Baryshkov 
Signed-off-by: Konrad Dybcio 
Link: https://lore.kernel.org/r/20230829-topic-8550_usbphy-v3-1-34ec434194c5@linaro.org
Signed-off-by: Vinod Koul