linux-stable.git/drivers/phy, branch v6.18.2

phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits

2025-12-18T13:03:09+00:00

[ Upstream commit 51023cf6cc5db3423dea6620746d9087e336e024 ]

Fixup PHY deskew FIFO to prevent the phase of D2 lane going ahead of
other lanes.  It's worth noting this might only happen when dealing with
HDMI 2.0 rates.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Co-developed-by: Algea Cao 
Signed-off-by: Algea Cao 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-3-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth

2025-12-18T13:03:08+00:00

[ Upstream commit 8daaced9f5eeb4a2c8ca08b0a8286b6a498a8387 ]

Due to its relatively low frequency, a noise stemming from the 24MHz PLL
reference clock may traverse the low-pass loop filter of ROPLL, which
could potentially generate some HDMI flash artifacts.

Reduce ROPLL loop bandwidth in an attempt to mitigate the problem.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Co-developed-by: Algea Cao 
Signed-off-by: Algea Cao 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode

2025-12-18T13:03:08+00:00

[ Upstream commit 72126e9623e1696ea83c77ef6d0306a6263bdd6b ]

When making use of the clock provider functionality, the output clock
does normally match the TMDS character rate, which is what the PHY PLL
gets configured to.

However, this is only applicable for default color depth of 8 bpc.  For
higher depths, the output clock is further divided by the hardware
according to the formula:

  output_clock_rate = tmds_char_rate * 8 / bpc

Since the existence of the clock divider wasn't taken into account when
support for high bpc has been introduced, make the necessary adjustments
to report the correct clock rate.

Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management")
Reported-by: Andy Yan 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: freescale: Initialize priv->lock

2025-12-18T13:03:08+00:00

[ Upstream commit 95e5905698983df94069e185f9eb3c67c7cf75d5 ]

Initialize priv->lock to fix the following warning.

WARNING: CPU: 0 PID: 12 at kernel/locking/mutex.c:577 __mutex_lock+0x70c/0x8b8
 Modules linked in:
 Hardware name: Freescale i.MX8QM MEK (DT)
 Call trace:
  __mutex_lock+0x70c/0x8b8 (P)
  mutex_lock_nested+0x24/0x30
  imx_hsio_power_on+0x4c/0x764
  phy_power_on+0x7c/0x12c
  imx_pcie_host_init+0x1d0/0x4d4
  dw_pcie_host_init+0x188/0x4b0
  imx_pcie_probe+0x324/0x6f4
  platform_probe+0x5c/0x98
  really_probe+0xbc/0x29c
  __driver_probe_device+0x78/0x12c
  driver_probe_device+0xd8/0x160
  __device_attach_driver+0xb8/0x138
  bus_for_each_drv+0x84/0xe4
  __device_attach_async_helper+0xb8/0xdc
  async_run_entry_fn+0x34/0xe0
  process_one_work+0x220/0x694
  worker_thread+0x1c0/0x36c
  kthread+0x14c/0x224

Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support")
Signed-off-by: Xiaolei Wang 
Reviewed-by: Frank Li 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20250925013806.569658-1-xiaolei.wang@windriver.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562

2025-12-18T13:03:08+00:00

[ Upstream commit be866e68966d20bcc4a73708093d577176f99c0c ]

When PCIe link enters L1 PM substates, the PHY will turn off its
PLL for power-saving. However, it turns off the PLL too fast which
leads the PHY to be broken. According to the PHY document, we need
to delay PLL turnoff time.

Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
Signed-off-by: Shawn Lin 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/1763459526-35004-2-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3528

2025-12-18T13:03:08+00:00

[ Upstream commit a2a18e5da64f8da306fa97c397b4c739ea776f37 ]

When PCIe link enters L1 PM substates, the PHY will turn off its
PLL for power-saving. However, it turns off the PLL too fast which
leads the PHY to be broken. According to the PHY document, we need
to delay PLL turnoff time.

Fixes: bbcca4fac873 ("phy: rockchip: naneng-combphy: Add RK3528 support")
Signed-off-by: Shawn Lin 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/1763459526-35004-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe()

2025-12-18T13:03:08+00:00

[ Upstream commit 662bb179d3381c7c069e44bb177396bcaee31cc8 ]

If an error occurs after the reset_control_deassert(),
reset_control_assert() must be called, as already done in the remove
function.

Use devm_add_action_or_reset() to add the missing call and simplify the
.remove() function accordingly.

While at it, drop struct rcar_gen3_chan::rstc as it is not used aymore.

[claudiu.beznea: removed "struct reset_control *rstc = data;" from
 rcar_gen3_reset_assert(), dropped struct rcar_gen3_chan::rstc]

Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus")
Signed-off-by: Christophe JAILLET 
Reviewed-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Wolfram Sang 
Signed-off-by: Claudiu Beznea 
Link: https://patch.msgid.link/20251023135810.1688415-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

Merge tag 'phy-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2025-10-06T17:34:22+00:00

Pull phy updates from Vinod Koul:
 "The usual bunch of device support and update to drivers.

  New Support
   - Qualcomm SM8750 QMP PCIe PHY dual lane support, PMIV0104 eusb2
     repeater support, QCS8300 eDP PHY support
   - Renesas RZ/T2H and RZ/N2H support and updates to driver for that
   - TI TCAN1051 phy support
   - Rockchip rk3588 dphy support, RK3528 combphy support

  Updates:
   - cadence updates for calibration and polling for ready and enabling
     of lower resolutions, runtime pm support,
   - Rockchip: enable U3 otg port
   - Renesas USXGMII mode support
   - Qualcomm UFS PHY and PLL regulator load support"

* tag 'phy-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (64 commits)
  phy: rockchip: phy-rockchip-inno-csidphy: add support for rk3588 variant
  phy: rockchip: phy-rockchip-inno-csidphy: allow for different reset lines
  phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0
  dt-bindings: phy: rockchip-inno-csi-dphy: add rk3588 variant
  dt-bindings: phy: rockchip-inno-csi-dphy: make power-domains non-required
  phy: cadence: cdns-dphy: Enable lower resolutions in dphy
  phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet
  phy: renesas: r8a779f0-ether-serdes: add USXGMII mode
  phy: sophgo: Add USB 2.0 PHY driver for Sophgo CV18XX/SG200X
  dt-bindings: phy: Add Sophgo CV1800 USB phy
  phy: cadence: cdns-dphy: Update calibration wait time for startup state machine
  phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
  phy: renesas: rcar-gen3-usb2: Fix ID check logic with VBUS valid
  dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1051
  phy: lynx-28g: check return value when calling lynx_28g_pll_get
  phy: qcom: m31-eusb2: Fix the error log while enabling clock
  phy: rockchip: usbdp: Remove redundant ternary operators
  phy: renesas: rcar-gen3-usb2: Remove redundant ternary operators
  phy: hisilicon: Remove redundant ternary operators
  phy: qcom-qmp-ufs: Add PHY and PLL regulator load
  ...

Merge tag 'bitmap-for-6.18' of https://github.com/norov/linux

2025-10-02T15:57:03+00:00

Pull bitmap updates from Yury Norov:

 - FIELD_PREP_WM16() consolidation (Nicolas)

 - bitmaps for Rust (Burak)

 - __fls() fix for arc (Kees)

* tag 'bitmap-for-6.18' of https://github.com/norov/linux: (25 commits)
  rust: add dynamic ID pool abstraction for bitmap
  rust: add find_bit_benchmark_rust module.
  rust: add bitmap API.
  rust: add bindings for bitops.h
  rust: add bindings for bitmap.h
  phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro
  clk: sp7021: switch to FIELD_PREP_WM16 macro
  PCI: dw-rockchip: Switch to FIELD_PREP_WM16 macro
  PCI: rockchip: Switch to FIELD_PREP_WM16* macros
  net: stmmac: dwmac-rk: switch to FIELD_PREP_WM16 macro
  ASoC: rockchip: i2s-tdm: switch to FIELD_PREP_WM16_CONST macro
  drm/rockchip: dw_hdmi: switch to FIELD_PREP_WM16* macros
  phy: rockchip-usb: switch to FIELD_PREP_WM16 macro
  drm/rockchip: inno-hdmi: switch to FIELD_PREP_WM16 macro
  drm/rockchip: dw_hdmi_qp: switch to FIELD_PREP_WM16 macro
  phy: rockchip-samsung-dcphy: switch to FIELD_PREP_WM16 macro
  drm/rockchip: vop2: switch to FIELD_PREP_WM16 macro
  drm/rockchip: dsi: switch to FIELD_PREP_WM16* macros
  phy: rockchip-emmc: switch to FIELD_PREP_WM16 macro
  drm/rockchip: lvds: switch to FIELD_PREP_WM16 macro
  ...

phy: rockchip-pcie: switch to FIELD_PREP_WM16 macro

2025-09-22T19:52:44+00:00

The era of hand-rolled HIWORD_UPDATE macros is over, at least for those
drivers that use constant masks.

The Rockchip PCIe PHY driver, used on the RK3399, has its own definition
of HIWORD_UPDATE.

Remove it, and replace instances of it with hw_bitfield.h's
FIELD_PREP_WM16. To achieve this, some mask defines are reshuffled, as
FIELD_PREP_WM16 uses the mask as both the mask of bits to write and to
derive the shift amount from in order to shift the value.

In order to ensure that the mask is always a constant, the inst->index
shift is performed after the FIELD_PREP_WM16, as this is a runtime
value.

>From this, we gain compile-time error checking, and in my humble opinion
nicer code, as well as a single definition of this macro across the
entire codebase to aid in code comprehension.

Tested on a RK3399 ROCKPro64, where PCIe still works as expected when
accessing an NVMe drive.

Signed-off-by: Nicolas Frattaroli 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Yury Norov (NVIDIA)