linux-stable.git/drivers/phy, branch v4.14.151

phy: renesas: rcar-gen3-usb2: Disable clearing VBUS in over-current

2019-09-21T05:15:27+00:00

commit e6839c31a608e79f2057fab987dd814f5d3477e6 upstream.

The hardware manual should be revised, but the initial value of
VBCTRL.OCCLREN is set to 1 actually. If the bit is set, the hardware
clears VBCTRL.VBOUT and ADPCTRL.DRVVBUS registers automatically
when the hardware detects over-current signal from a USB power switch.
However, since the hardware doesn't have any registers which
indicates over-current, the driver cannot handle it at all. So, if
"is_otg_channel" hardware detects over-current, since ADPCTRL.DRVVBUS
register is cleared automatically, the channel cannot be used after
that.

To resolve this behavior, this patch sets the VBCTRL.OCCLREN to 0
to keep ADPCTRL.DRVVBUS even if the "is_otg_channel" hardware
detects over-current. (We assume a USB power switch itself protects
over-current and turns the VBUS off.)

This patch is inspired by a BSP patch from Kazuya Mizuguchi.

Fixes: 1114e2d31731 ("phy: rcar-gen3-usb2: change the mode to OTG on the combined channel")
Cc:  # v4.5+
Signed-off-by: Yoshihiro Shimoda 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Greg Kroah-Hartman

phy: renesas: rcar-gen2: Fix memory leak at error paths

2019-07-31T05:28:51+00:00

[ Upstream commit d4a36e82924d3305a17ac987a510f3902df5a4b2 ]

This patch fixes memory leak at error paths of the probe function.
In for_each_child_of_node, if the loop returns, the driver should
call of_put_node() before returns.

Reported-by: Julia Lawall 
Fixes: 1233f59f745b237 ("phy: Renesas R-Car Gen2 PHY driver")
Signed-off-by: Yoshihiro Shimoda 
Reviewed-by: Geert Uytterhoeven 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sasha Levin

phy: sun4i-usb: Make sure to disable PHY0 passby for peripheral mode

2019-05-31T13:47:26+00:00

[ Upstream commit e6f32efb1b128344a2c7df9875bc1a1abaa1d395 ]

On platforms where the MUSB and HCI controllers share PHY0, PHY passby
is required when using the HCI controller with the PHY, but it must be
disabled when the MUSB controller is used instead.

Without this, PHY0 passby is always enabled, which results in broken
peripheral mode on such platforms (e.g. H3/H5).

Fixes: ba4bdc9e1dc0 ("PHY: sunxi: Add driver for sunxi usb phy")

Signed-off-by: Paul Kocialkowski 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sasha Levin

phy: sun4i-usb: Support set_mode to USB_HOST for non-OTG PHYs

2019-04-03T04:25:19+00:00

commit 1396929e8a903db80425343cacca766a18ad6409 upstream.

While only the first PHY supports mode switching, the remaining PHYs
work in USB host mode. They should support set_mode with mode=USB_HOST
instead of failing. This is especially needed now that the USB core does
set_mode for all USB ports, which was added in commit b97a31348379 ("usb:
core: comply to PHY framework").

Make set_mode with mode=USB_HOST a no-op instead of failing for the
non-OTG USB PHYs.

Fixes: 6ba43c291961 ("phy-sun4i-usb: Add support for phy_set_mode")
Signed-off-by: Chen-Yu Tsai 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman

phy: tegra: remove redundant self assignment of 'map'

2019-02-27T09:08:09+00:00

commit a0dd6773038f3fd2bd1b4f7ec193887cffc49046 upstream.

The assignment of map to itself is redundant and can be removed.
Detected with Coccinelle.

Signed-off-by: Colin Ian King 
Signed-off-by: Kishon Vijay Abraham I 
Cc: Nathan Chancellor 
Signed-off-by: Greg Kroah-Hartman

phy: sun4i-usb: add support for missing USB PHY index

2019-02-12T18:46:03+00:00

[ Upstream commit 2659392e5c08dff626e6db1d739adff58a94604d ]

The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a
3.0 port with dedicated PHY) and USB2 (which doesn't exist at all).

Add support for this kind of missing USB PHY index.

Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sasha Levin

phy: phy-mtk-tphy: use auto instead of force to bypass utmi signals

2018-08-15T16:12:48+00:00

commit 00c0092c5f62147b7d85f0c6f1cf245a0a1ff3b6 upstream.

When system is running, if usb2 phy is forced to bypass utmi signals,
all PLL will be turned off, and it can't detect device connection
anymore, so replace force mode with auto mode which can bypass utmi
signals automatically if no device attached for normal flow.
But keep the force mode to fix RX sensitivity degradation issue.

Signed-off-by: Chunfeng Yun 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Amit Pundir 
Signed-off-by: Greg Kroah-Hartman

phy: qcom-qusb2: Fix crash if nvmem cell not specified

2018-06-16T07:45:16+00:00

commit 0b4555e776ba0712c6fafb98b226b21fd05d2427 upstream.

Driver currently crashes due to NULL pointer deference
while updating PHY tune register if nvmem cell is NULL.
Since, fused value for Tune1/2 register is optional,
we'd rather bail out.

Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Reviewed-by: Vivek Gautam 
Reviewed-by: Evan Green 
Cc: stable  # 4.14+
Signed-off-by: Manu Gautam 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Greg Kroah-Hartman

phy: qcom-qmp: Fix phy pipe clock gating

2018-05-30T05:52:36+00:00

[ Upstream commit f8ba22a39e985c93e278709b1d5f20857a26b49b ]

Pipe clock comes out of the phy and is available as long as
the phy is turned on. Clock controller fails to gate this
clock after the phy is turned off and generates a warning.

/ # [   33.048561] gcc_usb3_phy_pipe_clk status stuck at 'on'
[   33.048585] ------------[ cut here ]------------
[   33.052621] WARNING: CPU: 1 PID: 18 at ../drivers/clk/qcom/clk-branch.c:97 clk_branch_wait+0xf0/0x108
[   33.057384] Modules linked in:
[   33.066497] CPU: 1 PID: 18 Comm: kworker/1:0 Tainted: G        W       4.12.0-rc7-00024-gfe926e34c36d-dirty #96
[   33.069451] Hardware name: Qualcomm Technologies, Inc. DB820c (DT)
...
[   33.278565] [] clk_branch_wait+0xf0/0x108
[   33.286375] [] clk_branch2_disable+0x28/0x34
[   33.291761] [] clk_core_disable+0x5c/0x88
[   33.297660] [] clk_core_disable_lock+0x20/0x34
[   33.303129] [] clk_disable+0x1c/0x24
[   33.309384] [] qcom_qmp_phy_poweroff+0x20/0x48
[   33.314328] [] phy_power_off+0x80/0xdc
[   33.320492] [] dwc3_core_exit+0x94/0xa0
[   33.325784] [] dwc3_suspend_common+0x50/0x60
[   33.331080] [] dwc3_runtime_suspend+0x48/0x6c
[   33.336810] [] pm_generic_runtime_suspend+0x28/0x38
[   33.342627] [] __rpm_callback+0x150/0x254
[   33.349222] [] rpm_callback+0x24/0x78
[   33.354604] [] rpm_suspend+0xe0/0x4e4
[   33.359813] [] pm_runtime_work+0xdc/0xf0
[   33.365028] [] process_one_work+0x12c/0x28c
[   33.370576] [] worker_thread+0x58/0x3b8
[   33.376393] [] kthread+0x100/0x12c
[   33.381776] [] ret_from_fork+0x10/0x50

Fix this by disabling it as the first thing in phy_exit().

Fixes: e78f3d15e115 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Signed-off-by: Vivek Gautam 
Signed-off-by: Manu Gautam 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman

phy: rockchip-emmc: retry calpad busy trimming

2018-05-30T05:52:35+00:00

[ Upstream commit a4781c2a74b249cad814ceea7272997bbd20051e ]

It turns out that 5us isn't enough for all cases, so let's
retry some more times to wait for caldone.

Signed-off-by: Shawn Lin 
Tested-by: Ziyuan Xu 
Signed-off-by: Caesar Wang 
Reviewed-by: Douglas Anderson 
Signed-off-by: Kishon Vijay Abraham I 
Signed-off-by: Sasha Levin 
Signed-off-by: Greg Kroah-Hartman