linux-stable.git/drivers/phy, branch linux-6.17.y

phy: rockchip: samsung-hdptx: Prevent Inter-Pair Skew from exceeding the limits

2025-12-18T12:59:49+00:00

[ Upstream commit 51023cf6cc5db3423dea6620746d9087e336e024 ]

Fixup PHY deskew FIFO to prevent the phase of D2 lane going ahead of
other lanes.  It's worth noting this might only happen when dealing with
HDMI 2.0 rates.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Co-developed-by: Algea Cao 
Signed-off-by: Algea Cao 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-3-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: samsung-hdptx: Reduce ROPLL loop bandwidth

2025-12-18T12:59:49+00:00

[ Upstream commit 8daaced9f5eeb4a2c8ca08b0a8286b6a498a8387 ]

Due to its relatively low frequency, a noise stemming from the 24MHz PLL
reference clock may traverse the low-pass loop filter of ROPLL, which
could potentially generate some HDMI flash artifacts.

Reduce ROPLL loop bandwidth in an attempt to mitigate the problem.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Co-developed-by: Algea Cao 
Signed-off-by: Algea Cao 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-2-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: samsung-hdptx: Fix reported clock rate in high bpc mode

2025-12-18T12:59:49+00:00

[ Upstream commit 72126e9623e1696ea83c77ef6d0306a6263bdd6b ]

When making use of the clock provider functionality, the output clock
does normally match the TMDS character rate, which is what the PHY PLL
gets configured to.

However, this is only applicable for default color depth of 8 bpc.  For
higher depths, the output clock is further divided by the hardware
according to the formula:

  output_clock_rate = tmds_char_rate * 8 / bpc

Since the existence of the clock divider wasn't taken into account when
support for high bpc has been introduced, make the necessary adjustments
to report the correct clock rate.

Fixes: 9d0ec51d7c22 ("phy: rockchip: samsung-hdptx: Add high color depth management")
Reported-by: Andy Yan 
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20251028-phy-hdptx-fixes-v1-1-ecc642a59d94@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: freescale: Initialize priv->lock

2025-12-18T12:59:49+00:00

[ Upstream commit 95e5905698983df94069e185f9eb3c67c7cf75d5 ]

Initialize priv->lock to fix the following warning.

WARNING: CPU: 0 PID: 12 at kernel/locking/mutex.c:577 __mutex_lock+0x70c/0x8b8
 Modules linked in:
 Hardware name: Freescale i.MX8QM MEK (DT)
 Call trace:
  __mutex_lock+0x70c/0x8b8 (P)
  mutex_lock_nested+0x24/0x30
  imx_hsio_power_on+0x4c/0x764
  phy_power_on+0x7c/0x12c
  imx_pcie_host_init+0x1d0/0x4d4
  dw_pcie_host_init+0x188/0x4b0
  imx_pcie_probe+0x324/0x6f4
  platform_probe+0x5c/0x98
  really_probe+0xbc/0x29c
  __driver_probe_device+0x78/0x12c
  driver_probe_device+0xd8/0x160
  __device_attach_driver+0xb8/0x138
  bus_for_each_drv+0x84/0xe4
  __device_attach_async_helper+0xb8/0xdc
  async_run_entry_fn+0x34/0xe0
  process_one_work+0x220/0x694
  worker_thread+0x1c0/0x36c
  kthread+0x14c/0x224

Fixes: 82c56b6dd24f ("phy: freescale: imx8qm-hsio: Add i.MX8QM HSIO PHY driver support")
Signed-off-by: Xiaolei Wang 
Reviewed-by: Frank Li 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/20250925013806.569658-1-xiaolei.wang@windriver.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562

2025-12-18T12:59:49+00:00

[ Upstream commit be866e68966d20bcc4a73708093d577176f99c0c ]

When PCIe link enters L1 PM substates, the PHY will turn off its
PLL for power-saving. However, it turns off the PLL too fast which
leads the PHY to be broken. According to the PHY document, we need
to delay PLL turnoff time.

Fixes: f13bff25161b ("phy: rockchip-naneng-combo: Support rk3562")
Signed-off-by: Shawn Lin 
Reviewed-by: Neil Armstrong 
Link: https://patch.msgid.link/1763459526-35004-2-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: naneng-combphy: Add SoC prefix to register definitions

2025-12-18T12:59:49+00:00

[ Upstream commit b3bbc6afcff50e2fd4d51dd64929e62d66fdc814 ]

All supported variants of naneng-combphy follow a register layout
similar to the RK3568 variant with some exceptions of SoC-specific
registers.

Add RK3568 prefix for the common set of registers and the corresponding
SoC prefix for SoC-specific registers, making usage of definitions clear
and preparing for future COMBPHY variants with a different register
layout.

Signed-off-by: Yao Zi 
Reviewed-by: Heiko Stuebner 
Reviewed-by: Neil Armstrong 
Link: https://lore.kernel.org/r/20250728102947.38984-6-ziyao@disroot.org
Signed-off-by: Vinod Koul 
Stable-dep-of: be866e68966d ("phy: rockchip: naneng-combphy: Fix PCIe L1ss support RK3562")
Signed-off-by: Sasha Levin

phy: renesas: rcar-gen3-usb2: Fix an error handling path in rcar_gen3_phy_usb2_probe()

2025-12-18T12:59:48+00:00

[ Upstream commit 662bb179d3381c7c069e44bb177396bcaee31cc8 ]

If an error occurs after the reset_control_deassert(),
reset_control_assert() must be called, as already done in the remove
function.

Use devm_add_action_or_reset() to add the missing call and simplify the
.remove() function accordingly.

While at it, drop struct rcar_gen3_chan::rstc as it is not used aymore.

[claudiu.beznea: removed "struct reset_control *rstc = data;" from
 rcar_gen3_reset_assert(), dropped struct rcar_gen3_chan::rstc]

Fixes: 4eae16375357 ("phy: renesas: rcar-gen3-usb2: Add support to initialize the bus")
Signed-off-by: Christophe JAILLET 
Reviewed-by: Biju Das 
Reviewed-by: Geert Uytterhoeven 
Tested-by: Wolfram Sang 
Signed-off-by: Claudiu Beznea 
Link: https://patch.msgid.link/20251023135810.1688415-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: phy-rockchip-inno-csidphy: allow writes to grf register 0

2025-11-13T20:37:19+00:00

[ Upstream commit 8c7c19466c854fa86b82d2148eaa9bf0e6531423 ]

The driver for the Rockchip MIPI CSI-2 DPHY uses GRF register offset
value 0 to sort out undefined registers. However, the RK3588 CSIDPHY GRF
this offset is perfectly fine (in fact, register 0 is the only one in
this register file).
Introduce a boolean variable to indicate valid registers and allow writes
to register 0.

Reviewed-by: Neil Armstrong 
Signed-off-by: Michael Riesch 
Link: https://lore.kernel.org/r/20250616-rk3588-csi-dphy-v4-4-a4f340a7f0cf@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: renesas: r8a779f0-ether-serdes: add new step added to latest datasheet

2025-11-13T20:37:19+00:00

[ Upstream commit e4a8db93b5ec9bca1cc66b295544899e3afd5e86 ]

R-Car S4-8 datasheet Rev.1.20 describes some additional register
settings at the end of the initialization.

Signed-off-by: Michael Dege 
Link: https://lore.kernel.org/r/20250703-renesas-serdes-update-v4-2-1db5629cac2b@renesas.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: cadence: cdns-dphy: Enable lower resolutions in dphy

2025-11-13T20:37:19+00:00

[ Upstream commit 43bd2c44515f8ee5c019ce6e6583f5640387a41b ]

Enable support for data lane rates between 80-160 Mbps cdns dphy
as mentioned in TRM [0] by setting the pll_opdiv field to 16.
This change enables lower resolutions like 640x480 at 60Hz.

[0]: https://www.ti.com/lit/zip/spruil1
(Table 12-552. DPHY_TX_PLL_CTRL Register Field Descriptions)

Reviewed-by: Udit Kumar 
Reviewed-by: Devarsh Thakkar 
Signed-off-by: Harikrishna Shenoy 
Link: https://lore.kernel.org/r/20250807052002.717807-1-h-shenoy@ti.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin