linux-stable.git/drivers/phy, branch linux-6.10.y

phy: phy-rockchip-samsung-hdptx: Explicitly include pm_runtime.h

2024-10-04T14:33:04+00:00

[ Upstream commit 1b369ff94bc36d2e16c8a91c0ea8ebd329555976 ]

Driver makes use of helpers from pm_runtime.h, but relies on the header
file being implicitly included.

Explicitly pull the header in to avoid potential build failures in some
configurations.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Reviewed-by: Heiko Stuebner 
Signed-off-by: Cristian Ciocaltea 
Link: https://lore.kernel.org/r/20240620-rk3588-hdmiphy-clkprov-v2-1-6a2d2164e508@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: zynqmp: Take the phy mutex in xlate

2024-09-12T09:12:58+00:00

[ Upstream commit d79c6840917097285e03a49f709321f5fb972750 ]

Take the phy mutex in xlate to protect against concurrent
modification/access to gtr_phy. This does not typically cause any
issues, since in most systems the phys are only xlated once and
thereafter accessed with the phy API (which takes the locks). However,
we are about to allow userspace to access phys for debugging, so it's
important to avoid any data races.

Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20240628205540.3098010-5-sean.anderson@linux.dev
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: xilinx: phy-zynqmp: Fix SGMII linkup failure on resume

2024-09-04T11:30:07+00:00

[ Upstream commit 5af9b304bc6010723c02f74de0bfd24ff19b1a10 ]

On a few Kria KR260 Robotics Starter Kit the PS-GEM SGMII linkup is not
happening after the resume. This is because serdes registers are reset
when FPD is off (in suspend state) and needs to be reprogrammed in the
resume path with the same default initialization as done in the first
stage bootloader psu_init routine.

To address the failure introduce a set of serdes registers to be saved in
the suspend path and then restore it on resume.

Fixes: 4a33bea00314 ("phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver")
Signed-off-by: Piyush Mehta 
Signed-off-by: Radhey Shyam Pandey 
Link: https://lore.kernel.org/r/1722837547-2578381-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisation

2024-09-04T11:30:07+00:00

[ Upstream commit 0e8a0504da59041e775a95db3ebc1a6211423593 ]

Update the PCIe Gen4 PHY init sequence with the latest based on internal
Qualcomm documentation.

Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE")
Signed-off-by: Abel Vesa 
Link: https://lore.kernel.org/r/20240801-x1e80100-phy-qmp-pcie-fix-config-v2-1-cdc0f22b4169@linaro.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: fsl-imx8mq-usb: fix tuning parameter name

2024-09-04T11:30:06+00:00

commit ce52c2532299c7ccfd34a52db8d071e890a78c59 upstream.

According to fsl,imx8mq-usb-phy.yaml, this tuning parameter should be
fsl,phy-pcs-tx-deemph-3p5db-attenuation-db.

Fixes: 63c85ad0cd81 ("phy: fsl-imx8mp-usb: add support for phy tuning")
Cc: stable@vger.kernel.org
Signed-off-by: Xu Yang 
Reviewed-by: Alexander Stein 
Link: https://lore.kernel.org/r/20240801124642.1152838-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul 
Signed-off-by: Greg Kroah-Hartman

phy: zynqmp: Enable reference clock correctly

2024-08-03T07:00:59+00:00

[ Upstream commit 687d6bccb28238fcfa65f7c1badfdfeac498c428 ]

Lanes can use other lanes' reference clocks, as determined by refclk.
Use refclk to determine the clock to enable/disable instead of always
using the lane's own reference clock. This ensures the clock selected in
xpsgtr_configure_pll is the one enabled.

For the other half of the equation, always program REF_CLK_SEL even when
we are selecting the lane's own clock. This ensures that Linux's idea of
the reference clock matches the hardware. We use the "local" clock mux
for this instead of going through the ref clock network.

Fixes: 25d700833513 ("phy: xilinx: phy-zynqmp: dynamic clock support for power-save")
Signed-off-by: Sean Anderson 
Link: https://lore.kernel.org/r/20240628205540.3098010-2-sean.anderson@linux.dev
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: cadence-torrent: Check return value on register read

2024-08-03T07:00:59+00:00

[ Upstream commit 967969cf594ed3c1678a9918d6e9bb2d1591cbe9 ]

cdns_torrent_dp_set_power_state() does not consider that ret might be
overwritten. Add return value check of regmap_read_poll_timeout() after
register read in cdns_torrent_dp_set_power_state().

Fixes: 5b16a790f18d ("phy: cadence-torrent: Reorder few functions to remove function declarations")
Signed-off-by: Ma Ke 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20240702032042.3993031-1-make24@iscas.ac.cn
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON

2024-08-03T07:00:59+00:00

[ Upstream commit edf9e04955d2387032beac54ebf20b43aaca2adf ]

Compile testing configurations without REGMAP support enabled results in
a bunch of errors being reported:

  ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:569:21: error: variable ‘rk_hdptx_phy_regmap_config’ has initializer but incomplete type
    569 | static const struct regmap_config rk_hdptx_phy_regmap_config = {
        |                     ^~~~~~~~~~~~~
  ../drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c:570:10: error: ‘const struct regmap_config’ has no member named ‘reg_bits’
    570 |         .reg_bits = 32,
        |          ^~~~~~~~

Note that selecting REGMAP alone is not enough, because of the following
liker error:

  phy-rockchip-samsung-hdptx.c:(.text+0x10c): undefined reference to `__devm_regmap_init_mmio_clk'

Instead of the obvious fix to enable REGMAP_MMIO, select MFD_SYSCON,
which implicitly enables REGMAP_MMIO as well.  The rationale is that the
driver has been already relying on the syscon functionality.

Moreover, without MFD_SYSCON enabled, the test coverage is reduced,
since the linker might not detect any potential undefined references
following syscon_regmap_lookup_by_phandle() invocation in
rk_hdptx_phy_probe() body.  That is because the function would
unconditionally return -ENOTSUP, hence the compiler is free to optimize
out any unreachable code.

Finally ensure PHY_ROCKCHIP_SAMSUNG_HDPTX depends on HAS_IOMEM, as
required by MFD_SYSCON.

Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Signed-off-by: Cristian Ciocaltea 
Link: https://lore.kernel.org/r/20240629-rk-hdptx-compile-test-fix-v1-1-c86675ba8070@collabora.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: qcom: qmp-pcie: restore compatibility with existing DTs

2024-08-03T07:00:58+00:00

[ Upstream commit 912cee11c14376a6f707d72fcaf343a40bff48e8 ]

Existing device trees specify only a single clock-output-name for the
PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
that property. When it doesn't find it, it returns an error, thus
failing the probe of the PHY and thus breaking support for the
corresponding PCIe host.

Follow the approach of the combo USB+DT PHY and generate the name for
the AUX clocks instead of requiring it in DT.

Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
Reviewed-by: Neil Armstrong 
Signed-off-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsets

2024-06-03T14:00:47+00:00

Currently, none of the X1E80100 supported boards upstream have enabled
DP. As for USB, the reason it is not broken when it's obvious that the
offsets are wrong is because the only difference with respect to USB is
the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME
while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to
work, the DP serdes tables need to be added as they have different
values for V6 N4 when compared to V6 ones, even though they use the same
V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as
well.

Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh 
Signed-off-by: Kuogee Hsieh 
Signed-off-by: Abel Vesa 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul