linux-stable.git/drivers/phy/ti, branch linux-6.3.y

phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()

2023-05-11T14:17:35+00:00

[ Upstream commit 57c0e1362fdd57d0cea7ab1e583b58abf4bd8c2d ]

In the wiz_mode_select() function, the configuration performed for
PHY_TYPE_USXGMII is unreachable. Fix it.

Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver")
Signed-off-by: Siddharth Vadapalli 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

Merge tag 'phy-fixes-6.2' into next

2023-02-14T13:55:45+00:00

Merge fixes tag pulled into mainline by Linus into phy/next due to
dependency on amlogic patches

phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap

2023-01-18T17:15:35+00:00

The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.

The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.

Signed-off-by: Sinthu Raja 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20230113150615.19375-3-sinthu.raja@ti.com
Signed-off-by: Vinod Koul

phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified

2023-01-18T17:15:35+00:00

It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.

Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.

Signed-off-by: Sinthu Raja 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20230113150615.19375-2-sinthu.raja@ti.com
Signed-off-by: Vinod Koul

phy: ti: fix Kconfig warning and operator precedence

2023-01-11T07:54:33+00:00

Fix Kconfig depends operator precedence to prevent a Kconfig warning:

WARNING: unmet direct dependencies detected for MUX_MMIO
  Depends on [n]: MULTIPLEXER [=m] && OF [=n]
  Selected by [m]:
  - PHY_AM654_SERDES [=m] && (OF [=n] && ARCH_K3 || COMPILE_TEST [=y]) && COMMON_CLK [=y]

Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC")
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC")
Signed-off-by: Randy Dunlap 
Cc: Vinod Koul 
Cc: Kishon Vijay Abraham I 
Cc: linux-phy@lists.infradead.org
Cc: Arnd Bergmann 
Link: https://lore.kernel.org/r/20230110062529.22668-1-rdunlap@infradead.org
Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support

2022-11-24T18:11:41+00:00

Add support for j721s2-wiz-10g device which is similar to j721e-wiz-10g but
uses clock-names interface versus explicitly defining clock nodes within
device tree node.

Signed-off-by: Matt Ranostay 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20221123032413.1193961-3-mranostay@ti.com
Signed-off-by: Vinod Koul

phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e

2022-11-07T04:50:25+00:00

Each of the CPSW9G ports in J721e support additional modes like QSGMII.
Add a new compatible for J721e to support the additional modes.

In TI's J721e, each of the CPSW9G ethernet interfaces can act as a
QSGMII main or QSGMII-SUB port. The QSGMII main interface is responsible
for performing auto-negotiation between the MAC and the PHY while the rest
of the interfaces are designated as QSGMII-SUB interfaces, indicating that
they will not be taking part in the auto-negotiation process.

Signed-off-by: Siddharth Vadapalli 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20221026074532.109220-4-s-vadapalli@ti.com
Signed-off-by: Vinod Koul

phy: ti: gmii-sel: Update methods for fetching and using qsgmii main port

2022-11-07T04:50:25+00:00

The number of QSGMII main ports are specific to the device. TI's J7200 for
which the QSGMII main port property is fetched from the device-tree has
only one QSGMII main port. However, devices like TI's J721e support up to
two QSGMII main ports. Thus, the existing methods for fetching and using
the QSGMII main port are not scalable.

Update the existing methods for handling the QSGMII main ports and its
associated requirements to make it scalable for future devices.

Signed-off-by: Siddharth Vadapalli 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/20221026074532.109220-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: add j784s4-wiz-10g module support

2022-10-17T05:29:11+00:00

Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.

Acked-by: Roger Quadros 
Signed-off-by: Matt Ranostay 
Link: https://lore.kernel.org/r/20221015201123.195477-3-mranostay@ti.com
Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()

2022-09-24T06:29:37+00:00

These two error paths need to call of_node_put(child_node) before
returning.

Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g")
Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver")
Signed-off-by: Dan Carpenter 
Reviewed-by: Roger Quadros 
Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili
Signed-off-by: Vinod Koul