linux-stable.git/drivers/phy/rockchip, branch linux-6.8.y

phy: rockchip: naneng-combphy: Fix mux on rk3588

2024-05-02T14:35:33+00:00

[ Upstream commit d16d4002fea69b6609b852dd8db1f5844c02fbe4 ]

The pcie1l0_sel and pcie1l1_sel bits in PCIESEL_CON configure the
mux for PCIe1L0 and PCIe1L1 to either the PIPE Combo PHYs or the
PCIe3 PHY. Thus this configuration interfers with the data-lanes
configuration done by the PCIe3 PHY.

RK3588 has three Combo PHYs. The first one has a dedicated PCIe
controller and is not affected by this. For the other two Combo
PHYs, there is one mux for each of them.

pcie1l0_sel selects if PCIe 1L0 is muxed to Combo PHY 1 when
bit is set to 0 or to the PCIe3 PHY when bit is set to 1.

pcie1l1_sel selects if PCIe 1L1 is muxed to Combo PHY 2 when
bit is set to 0 or to the PCIe3 PHY when bit is set to 1.

Currently the code always muxes 1L0 and 1L1 to the Combi PHYs
once one of them is being used in PCIe mode. This is obviously
wrong when at least one of the ports should be muxed to the
PCIe3 PHY.

Fix this by introducing Combo PHY identification and then only
setting up the required bit.

Fixes: a03c44277253 ("phy: rockchip: Add naneng combo phy support for RK3588")
Reported-by: Michal Tomek 
Signed-off-by: Sebastian Reichel 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-3-9907136eeafd@kernel.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON bits

2024-05-02T14:35:33+00:00

[ Upstream commit 55491a5fa163bf15158f34f3650b3985f25622b9 ]

Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but
does not clear them because of an incorrect write mask. This fixes up
the issue by using a newly introduced constant for the write mask.

While at it also introduces a proper GENMASK based constant for the
PCIE30_PHY_MODE.

Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
Signed-off-by: Sebastian Reichel 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip-snps-pcie3: fix bifurcation on rk3588

2024-05-02T14:35:33+00:00

[ Upstream commit f8020dfb311d2b6cf657668792aaa5fa8863a7dd ]

So far all RK3588 boards use fully aggregated PCIe. CM3588 is one
of the few boards using this feature and apparently it is broken.

The PHY offers the following mapping options:

  port 0 lane 0 - always mapped to controller 0 (4L)
  port 0 lane 1 - to controller 0 or 2 (1L0)
  port 1 lane 0 - to controller 0 or 1 (2L)
  port 1 lane 1 - to controller 0, 1 or 3 (1L1)

The data-lanes DT property maps these as follows:

  0 = no controller (unsupported by the HW)
  1 = 4L
  2 = 2L
  3 = 1L0
  4 = 1L1

That allows the following configurations with first column being the
mainline data-lane mapping, second column being the downstream name,
third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register
values and final column being the user visible lane setup:

  <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation)
  <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.)
  <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0)
  <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1)
  <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports)

The driver currently does not program PHP_GRF_PCIESEL correctly, which
is fixed by this patch. As a side-effect the new logic is much simpler
than the old logic.

Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
Signed-off-by: Michal Tomek 
Signed-off-by: Sebastian Reichel 
Acked-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: phy-rockchip-inno-usb2: Add RK3128 support

2023-11-27T13:06:29+00:00

Add registers to support the 2-port usb2 phy found in RK312x SoC familiy.

Signed-off-by: Alex Bee 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20231119121340.109025-3-knaerzche@gmail.com
Signed-off-by: Vinod Koul

phy: rockchip-inno-usb2: Split ID interrupt phy registers

2023-11-27T13:06:29+00:00

Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID
detection interrupt registers. However the current implementation assumes
that falling and rising edge interrupt are always enabled in registers
spanning over subsequent bits.
That is not the case for RK3128's version of the phy and this
implementation can't be used as-is, since there are bits with different
purpose in between.

This splits up the register definitions for id_det_en, id_det_en and
id_det_clr registers in rising and falling edge variants.
It's required as preparation to support RK3128's Innosilicon usb2 phy as
well in this driver and matches pretty much to what the vendor does, so I'm
not expecting issues for other SoCs with that change.

Signed-off-by: Alex Bee 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20231119121340.109025-2-knaerzche@gmail.com
Signed-off-by: Vinod Koul

phy: rockchip-inno-usb2: Drop unnecessary DT includes

2023-10-13T10:16:09+00:00

Neither of_address.h or of_platform.h are used in the driver, so drop them.

Signed-off-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20231009172923.2457844-17-robh@kernel.org
Signed-off-by: Vinod Koul

phy: Use device_get_match_data()

2023-10-13T10:15:40+00:00

Use preferred device_get_match_data() instead of of_match_device() to
get the driver match data. With this, adjust the includes to explicitly
include the correct headers.

Signed-off-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20231009172923.2457844-15-robh@kernel.org
Signed-off-by: Vinod Koul

phy: rockchip: inno-dsidphy: Add rv1126 support

2023-08-22T13:58:11+00:00

Add support for Rockchip RV1126 DSI-DPHY.

The existing 2.5GHz phy timing table added for RK3568 is working
as it is for RV1126 as well.

Signed-off-by: Jagan Teki 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20230731110012.2913742-5-jagan@edgeble.ai
Signed-off-by: Vinod Koul

phy: Explicitly include correct DT includes

2023-07-17T06:22:56+00:00

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Signed-off-by: Rob Herring 
Acked-by: Marc Kleine-Budde  # for drivers/phy/phy-can-transceiver.c
Acked-by: Heiko Stuebner 
Acked-by: Sergio Paracuellos 
Link: https://lore.kernel.org/r/20230714174841.4061919-1-robh@kernel.org
Signed-off-by: Vinod Koul

phy/rockchip: inno-hdmi: add more supported pre-pll rates

2023-07-12T16:57:43+00:00

This adds a bunch of new pixel clock- and tmds rates to the pre-pll
table which are required to get more VESA and some DMT rates working.

It has been completely re-calculated to match the min- and max-vco of
(750 MHz - 3.2 GHz) requirements. If more than one configuration would
have been possible the lowest fbdiv and refdiv (and therefore lowest
vco rate) has been preferred.

It's important to note, that RK3228 version of the phy does not support
fractional dividers. To support the most possible rates for this version
also in both 8-bit and 10-bit variant, some rates are not exact. The
maximum deviation of the pixel clock is 0.26, which perfectly fits into
VESA DMT recommendation of 0.5%.

I tested all possible rates on several screens from different
manufacturers with both RK3228 and RK3328. Both pre- and post-PLL
locking are slighlty faster now.

Signed-off-by: Alex Bee 
Signed-off-by: Jonas Karlman 
Link: https://lore.kernel.org/r/20230615171005.2251032-7-jonas@kwiboo.se
Signed-off-by: Vinod Koul