linux-stable.git/drivers/phy/rockchip, branch linux-6.14.y

phy: phy-rockchip-samsung-hdptx: Fix PHY PLL output 50.25MHz error

2025-06-04T12:45:10+00:00

[ Upstream commit f9475055b11c0c70979bd1667a76b2ebae638eb7 ]

When using HDMI PLL frequency division coefficient at 50.25MHz
that is calculated by rk_hdptx_phy_clk_pll_calc(), it fails to
get PHY LANE lock. Although the calculated values are within the
allowable range of PHY PLL configuration.

In order to fix the PHY LANE lock error and provide the expected
50.25MHz output, manually compute the required PHY PLL frequency
division coefficient and add it to ropll_tmds_cfg configuration
table.

Signed-off-by: Algea Cao 
Reviewed-by: Cristian Ciocaltea 
Acked-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250427095124.3354439-1-algea.cao@rock-chips.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: phy-rockchip-samsung-hdptx: Swap the definitions of LCPLL_REF and ROPLL_REF

2025-05-29T09:13:24+00:00

[ Upstream commit 2947c8065e9efdd3b6434d2817dc8896234a3fc0 ]

According to the datasheet, setting the dig_clk_sel bit of CMN_REG(0097)
to 1'b1 selects LCPLL as the reference clock, while setting it to 1'b0
selects the ROPLL.

Signed-off-by: Damon Ding 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20250205105157.580060-2-damon.ding@rock-chips.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: usbdp: Only verify link rates/lanes/voltage when the corresponding set flags are set

2025-05-29T09:12:45+00:00

[ Upstream commit 969a38be437b68dc9e12e3c3f08911c9f9c8be73 ]

According documentation of phy_configure_opts_dp, at the configure
stage, link rates should only be verify/configure when set_rate
flag is set, the same applies to lanes and voltage.

So do it as the documentation says.
Because voltage setting depends on the lanes, link rates set
previously, so record the link rates and lanes at it's verify stage.

Signed-off-by: Andy Yan 
Link: https://lore.kernel.org/r/20250312080041.524546-1-andyshrk@163.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: usbdp: Avoid call hpd_event_trigger in dp_phy_init

2025-05-02T06:02:01+00:00

[ Upstream commit 28dc672a1a877c77b000c896abd8f15afcdc1b0c ]

Function rk_udphy_dp_hpd_event_trigger will set vogrf let it
trigger HPD interrupt to DP by Type-C. This configuration is only
required when the DP work in Alternate Mode, and called by
typec_mux_set. In standard DP mode, such settings will prevent
the DP from receiving HPD interrupts.

Signed-off-by: Andy Yan 
Link: https://lore.kernel.org/r/20250302115257.188774-1-andyshrk@163.com
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-id

2025-04-10T12:44:28+00:00

[ Upstream commit f08d1c08563846f9be79a4859e912c8795d690fd ]

The phy needs to know its identity in the system (phy0 or phy1 on rk3588)
for some actions and the driver currently contains code abusing of_alias
for that.

Devicetree aliases are always optional and should not be used for core
device functionality, so instead keep a list of phys on a soc in the
of_device_data and find the phy-id by comparing against the mapped
register-base.

Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support")
Signed-off-by: Heiko Stuebner 
Reviewed-by: Cristian Ciocaltea 
Reviewed-by: Sebastian Reichel 
Link: https://lore.kernel.org/r/20241206103401.1780416-3-heiko@sntech.de
Signed-off-by: Vinod Koul 
Signed-off-by: Sasha Levin

phy: rockchip: naneng-combphy: compatible reset with old DT

2025-02-04T05:12:37+00:00

The device tree of RK3568 did not specify reset-names before.
So add fallback to old behaviour to be compatible with old DT.

Fixes: fbcbffbac994 ("phy: rockchip: naneng-combphy: fix phy reset")
Cc: Jianfeng Liu 
Signed-off-by: Chukun Pan 
Reviewed-by: Jonas Karlman 
Link: https://lore.kernel.org/r/20250106100001.1344418-2-amadeus@jmu.edu.cn
Signed-off-by: Vinod Koul

phy: rockchip: fix Kconfig dependency more

2025-02-04T05:12:37+00:00

A previous patch ensured that USB Type C connector support is enabled,
but it is still possible to build the phy driver without enabling
CONFIG_USB (host support) or CONFIG_USB_GADGET (device support), and
in that case the common helper functions are unavailable:

aarch64-linux-ld: drivers/phy/rockchip/phy-rockchip-usbdp.o: in function `rk_udphy_probe':
phy-rockchip-usbdp.c:(.text+0xe74): undefined reference to `usb_get_maximum_speed'

Select CONFIG_USB_COMMON directly here, like we do in some other phy
drivers, to make sure this is available even when actual USB support
is disabled or in a loadable module that cannot be reached from a
built-in phy driver.

Fixes: 9c79b779643e ("phy: rockchip: fix CONFIG_TYPEC dependency")
Signed-off-by: Arnd Bergmann 
Reviewed-by: Sebastian Reichel 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20250122065249.1390081-1-arnd@kernel.org
Signed-off-by: Vinod Koul

Merge tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2025-01-29T22:32:38+00:00

Pull phy updates from Vinod Koul:
 "Lots of Qualcomm and Rockchip device support.

  New Support:
   - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and
     PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY
   - Rockchip rk3576 combo phy support

  Updates:
   - Drop Shengyang for JH7110 maintainer
   - Freescale hdmi register calculation optimization
   - Rockchip pcie phy mutex and regmap updates"

* tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits)
  dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY
  phy: rockchip: phy-rockchip-typec: Fix Copyright description
  dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs
  phy: qcom-qusb2: Add support for QCS615
  dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings
  phy: core: Simplify API of_phy_simple_xlate() implementation
  phy: sun4i-usb: Remove unused of_gpio.h
  phy: HiSilicon: Don't use "proxy" headers
  phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle()
  phy: qualcomm: qmp-pcie: add support for SAR2130P
  phy: qualcomm: qmp-pcie: define several new registers
  phy: qualcomm: qmp-pcie: split PCS_LANE1 region
  phy: qualcomm: qmp-combo: add support for SAR2130P
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible
  phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
  phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found
  phy: freescale: fsl-samsung-hdmi: Expand Integer divider range
  phy: rockchip-naneng-combo: add rk3576 support
  dt-bindings: phy: rockchip: add rk3576 compatible
  ...

phy: rockchip: phy-rockchip-typec: Fix Copyright description

2024-12-24T19:47:33+00:00

The company name has update to Rockchip Electronics Co., Ltd.
since 2021.
And change Co.Ltd to Co., Ltd. to fix mail server warning:
DBL_SPAM(6.50)[co.ltd:url];

Signed-off-by: Andy Yan 
Reviewed-by: Kever Yang 
Acked-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20241216100739.3726293-1-andyshrk@163.com
Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Set drvdata before enabling runtime PM

2024-12-08T16:12:07+00:00

In some cases, rk_hdptx_phy_runtime_resume() may be invoked before
platform_set_drvdata() is executed in ->probe(), leading to a NULL
pointer dereference when using the return of dev_get_drvdata().

Ensure platform_set_drvdata() is called before devm_pm_runtime_enable().

Reported-by: Dmitry Osipenko 
Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver")
Signed-off-by: Cristian Ciocaltea 
Reviewed-by: Heiko Stuebner 
Link: https://lore.kernel.org/r/20241023-phy-sam-hdptx-rpm-fix-v1-1-87f4c994e346@collabora.com
Signed-off-by: Vinod Koul