linux-stable.git/drivers/phy/qualcomm, branch v6.14 Linux kernel stable tree Merge tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 2025-01-29T22:32:38+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-01-29T22:32:38+00:00 9f10e7fb6a06bce4f81de5fd0f2f0390f99e89e4 Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ... 
Pull phy updates from Vinod Koul:
 "Lots of Qualcomm and Rockchip device support.

  New Support:
   - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and
     PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY
   - Rockchip rk3576 combo phy support

  Updates:
   - Drop Shengyang for JH7110 maintainer
   - Freescale hdmi register calculation optimization
   - Rockchip pcie phy mutex and regmap updates"

* tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits)
  dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY
  phy: rockchip: phy-rockchip-typec: Fix Copyright description
  dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs
  phy: qcom-qusb2: Add support for QCS615
  dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings
  phy: core: Simplify API of_phy_simple_xlate() implementation
  phy: sun4i-usb: Remove unused of_gpio.h
  phy: HiSilicon: Don't use "proxy" headers
  phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle()
  phy: qualcomm: qmp-pcie: add support for SAR2130P
  phy: qualcomm: qmp-pcie: define several new registers
  phy: qualcomm: qmp-pcie: split PCS_LANE1 region
  phy: qualcomm: qmp-combo: add support for SAR2130P
  dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible
  dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible
  phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
  phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found
  phy: freescale: fsl-samsung-hdmi: Expand Integer divider range
  phy: rockchip-naneng-combo: add rk3576 support
  dt-bindings: phy: rockchip: add rk3576 compatible
  ...
phy: qcom-qusb2: Add support for QCS615 2024-12-24T14:32:50+00:00 Krishna Kurapati krishna.kurapati@oss.qualcomm.com 2024-12-24T08:46:20+00:00 8adbf20e05025f588d68fb5b0fbbdab4e9a6f97e Add init sequence and phy configuration for QCS615. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224084621.4139021-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add init sequence and phy configuration for QCS615.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224084621.4139021-3-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qualcomm: qmp-pcie: add support for SAR2130P 2024-12-08T16:00:08+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-10-21T10:33:12+00:00 0fd0b31965b0d4a2caa9267c7aee43f1f78870e8 Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-6-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-6-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qualcomm: qmp-pcie: define several new registers 2024-12-08T16:00:08+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-10-21T10:33:11+00:00 8114f34dd0baa972085280610ad5be89a41d1414 Define several registers to be used by PCIe QMP PHYs on v6 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Define several registers to be used by PCIe QMP PHYs on v6 platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qualcomm: qmp-pcie: split PCS_LANE1 region 2024-12-08T16:00:08+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-10-21T10:33:10+00:00 f9d35dd39bf44d01012119b146a27c29e55d8ad8 The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled
this way as it simplified handled of devices with the old bindings.
Nowadays it can be handled as is, without hacks.

Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qualcomm: qmp-combo: add support for SAR2130P 2024-12-08T16:00:08+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-10-21T10:33:09+00:00 545069bcf39e9f025e8e3d749505e52423433e37 Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform. It mosly follows the SM8550 QMP PHY, but the QSERDES programming differs, most likely because of the parent clock rate differences. NOTE: The DP part wasn't yet tested, but it is not possible to support just the USB part of the PHY. DP part might require additional fixes later. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-3-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform.
It mosly follows the SM8550 QMP PHY, but the QSERDES programming
differs, most likely because of the parent clock rate differences.

NOTE: The DP part wasn't yet tested, but it is not possible to support
just the USB part of the PHY. DP part might require additional fixes
later.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-3-d883acf170f7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Fix register name in RX Lane config of SC8280XP 2024-12-04T14:32:27+00:00 Krishna Kurapati quic_kriskura@quicinc.com 2024-11-12T09:28:31+00:00 8886fb3240931a0afce82dea87edfe46bcb0a586 In RX Lane configuration sequence of SC8280XP, the register V5_RX_UCDR_FO_GAIN is incorrectly spelled as RX_UCDR_SO_GAIN and hence the programming sequence is wrong. Fix the register sequence accordingly to avoid any compliance failures. This has been tested on SA8775P by checking device mode enumeration in SuperSpeed. Cc: stable@vger.kernel.org Fixes: c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy") Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112092831.4110942-1-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
In RX Lane configuration sequence of SC8280XP, the register
V5_RX_UCDR_FO_GAIN is incorrectly spelled as RX_UCDR_SO_GAIN and
hence the programming sequence is wrong. Fix the register sequence
accordingly to avoid any compliance failures. This has been tested
on SA8775P by checking device mode enumeration in SuperSpeed.

Cc: stable@vger.kernel.org
Fixes: c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy")
Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241112092831.4110942-1-quic_kriskura@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom: qmp: Enable IPQ5424 support 2024-12-04T14:29:30+00:00 Varadarajan Narayanan quic_varada@quicinc.com 2024-11-18T05:28:37+00:00 b8ef065c13872f5a4155e71c338597fde683cfd6 Enable QMP USB3 phy support for IPQ5424 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241118052839.382431-5-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Enable QMP USB3 phy support for IPQ5424 SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241118052839.382431-5-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qusb2: add QUSB2 support for IPQ5424 2024-12-04T14:29:29+00:00 Varadarajan Narayanan quic_varada@quicinc.com 2024-11-18T05:28:35+00:00 9c56a1de296e70d16f1daac203d420378743a363 Add the phy init sequence for the Super Speed ports found on IPQ5424. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241118052839.382431-3-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the phy init sequence for the Super Speed ports found
on IPQ5424.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20241118052839.382431-3-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIe 2024-12-04T13:41:17+00:00 Krishna chaitanya chundru quic_krichai@quicinc.com 2024-11-22T02:33:10+00:00 21364b0fe378646fa301f29f714140a1f465561b Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform.

Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>