linux-stable.git/drivers/phy/qualcomm, branch v6.11 Linux kernel stable tree phy: qcom: qmp-pcie: Fix X1E80100 PCIe Gen4 PHY initialisation 2024-08-04T16:40:41+00:00 Abel Vesa abel.vesa@linaro.org 2024-08-01T10:40:24+00:00 0e8a0504da59041e775a95db3ebc1a6211423593 Update the PCIe Gen4 PHY init sequence with the latest based on internal Qualcomm documentation. Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE") Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20240801-x1e80100-phy-qmp-pcie-fix-config-v2-1-cdc0f22b4169@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Update the PCIe Gen4 PHY init sequence with the latest based on internal
Qualcomm documentation.

Fixes: 606060ce8fd0 ("phy: qcom-qmp-pcie: Add support for X1E80100 g3x2 and g4x2 PCIE")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240801-x1e80100-phy-qmp-pcie-fix-config-v2-1-cdc0f22b4169@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Merge tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 2024-07-24T20:11:28+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-07-24T20:11:28+00:00 c33ffdb70cc6df4105160f991288e7d2567d7ffa Pull phy updates from Vinod Koul: "New Support - Samsung Exynos gs101 drd combo phy - Qualcomm SC8180x USB uniphy, IPQ9574 QMP PCIe phy - Airoha EN7581 PCIe phy - Freescale i.MX8Q HSIO SerDes phy - Starfive jh7110 dphy tx Updates: - Resume support for j721e-wiz driver - Updates to Exynos usbdrd driver - Support for optional power domains in g12a usb2-phy driver - Debugfs support and updates to zynqmp driver" * tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (56 commits) phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema dt-bindings: phy: qcom,qmp-usb: fix spelling error phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS) phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk phy: exynos5-usbdrd: convert core clocks to clk_bulk phy: exynos5-usbdrd: support isolating HS and SS ports independently dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible phy: core: Fix documentation of of_phy_get phy: starfive: Correct the dphy configure process phy: zynqmp: Add debugfs support phy: zynqmp: Take the phy mutex in xlate phy: zynqmp: Only wait for PLL lock "primary" instances phy: zynqmp: Store instance instead of type phy: zynqmp: Enable reference clock correctly phy: cadence-torrent: Check return value on register read phy: Fix the cacography in phy-exynos5250-usb2.c phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON ... 
Pull phy updates from Vinod Koul:
 "New Support
   - Samsung Exynos gs101 drd combo phy
   - Qualcomm SC8180x USB uniphy, IPQ9574 QMP PCIe phy
   - Airoha EN7581 PCIe phy
   - Freescale i.MX8Q HSIO SerDes phy
   - Starfive jh7110 dphy tx

  Updates:
   - Resume support for j721e-wiz driver
   - Updates to Exynos usbdrd driver
   - Support for optional power domains in g12a usb2-phy driver
   - Debugfs support and updates to zynqmp driver"

* tag 'phy-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (56 commits)
  phy: airoha: Add dtime and Rx AEQ IO registers
  dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers
  dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema
  dt-bindings: phy: qcom,qmp-usb: fix spelling error
  phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)
  phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk
  phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
  phy: exynos5-usbdrd: convert core clocks to clk_bulk
  phy: exynos5-usbdrd: support isolating HS and SS ports independently
  dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible
  phy: core: Fix documentation of of_phy_get
  phy: starfive: Correct the dphy configure process
  phy: zynqmp: Add debugfs support
  phy: zynqmp: Take the phy mutex in xlate
  phy: zynqmp: Only wait for PLL lock "primary" instances
  phy: zynqmp: Store instance instead of type
  phy: zynqmp: Enable reference clock correctly
  phy: cadence-torrent: Check return value on register read
  phy: Fix the cacography in phy-exynos5250-usb2.c
  phy: phy-rockchip-samsung-hdptx: Select CONFIG_MFD_SYSCON
  ...
phy: qcom: qmp-pcie: restore compatibility with existing DTs 2024-06-15T11:31:16+00:00 Dmitry Baryshkov dmitry.baryshkov@linaro.org 2024-06-14T10:18:24+00:00 912cee11c14376a6f707d72fcaf343a40bff48e8 Existing device trees specify only a single clock-output-name for the PCIe PHYs. The function phy_aux_clk_register() expects a second entry in that property. When it doesn't find it, it returns an error, thus failing the probe of the PHY and thus breaking support for the corresponding PCIe host. Follow the approach of the combo USB+DT PHY and generate the name for the AUX clocks instead of requiring it in DT. Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Existing device trees specify only a single clock-output-name for the
PCIe PHYs. The function phy_aux_clk_register() expects a second entry in
that property. When it doesn't find it, it returns an error, thus
failing the probe of the PHY and thus breaking support for the
corresponding PCIe host.

Follow the approach of the combo USB+DT PHY and generate the name for
the AUX clocks instead of requiring it in DT.

Fixes: 583ca9ccfa80 ("phy: qcom: qmp-pcie: register second optional PHY AUX clock")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-1-730d1811acf4@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp-pcie: Add support for IPQ9574 g3x1 and g3x2 PCIEs 2024-06-03T14:02:33+00:00 devi priya quic_devipriy@quicinc.com 2024-05-16T03:24:36+00:00 2f2f5c13cc5ea87f1dd2debfd06fe5f624e5c0fd Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm IPQ9574 platform. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add support for a single-lane and two-lane PCIe PHYs
found on Qualcomm IPQ9574 platform.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20240516032436.2681828-5-quic_devipriy@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add missing register definitions for PCS V5 2024-06-03T14:02:32+00:00 devi priya quic_devipriy@quicinc.com 2024-05-16T03:24:35+00:00 71ae2acf1d7542ecd21c6933cae8fe65d550074b Add missing register offsets for PCS V5 registers. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add missing register offsets for PCS V5 registers.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20240516032436.2681828-4-quic_devipriy@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add missing offsets for Qserdes PLL registers. 2024-06-03T14:02:32+00:00 devi priya quic_devipriy@quicinc.com 2024-05-16T03:24:34+00:00 f1aaa788b997ba8a7810da0696e89fd3f79ecce3 Add missing register offsets for Qserdes PLL. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: devi priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add missing register offsets for Qserdes PLL.

Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Link: https://lore.kernel.org/r/20240516032436.2681828-3-quic_devipriy@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom: qmp-combo: Switch from V6 to V6 N4 register offsets 2024-06-03T14:00:47+00:00 Abel Vesa abel.vesa@linaro.org 2024-05-27T07:20:37+00:00 163c1a356a847ab4767200fd4a45b3f8e4ddc900 Currently, none of the X1E80100 supported boards upstream have enabled DP. As for USB, the reason it is not broken when it's obvious that the offsets are wrong is because the only difference with respect to USB is the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to work, the DP serdes tables need to be added as they have different values for V6 N4 when compared to V6 ones, even though they use the same V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as well. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Currently, none of the X1E80100 supported boards upstream have enabled
DP. As for USB, the reason it is not broken when it's obvious that the
offsets are wrong is because the only difference with respect to USB is
the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME
while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to
work, the DP serdes tables need to be added as they have different
values for V6 N4 when compared to V6 ones, even though they use the same
V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as
well.

Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: pcs: Add missing v6 N4 register offsets 2024-06-03T14:00:47+00:00 Abel Vesa abel.vesa@linaro.org 2024-05-27T07:20:36+00:00 99bf89626335bbec71d8461f0faec88551440850 The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for combo USB and DP PHY. Currently, the X1E80100 uses the pure V6 PCS register offsets, which are different. Add the offsets so the mentioned platform can be fixed later on. Add the new PCS offsets in a dedicated header file. Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The new X1E80100 SoC bumps up the HW version of QMP phy to v6 N4 for
combo USB and DP PHY.  Currently, the X1E80100 uses the pure V6 PCS
register offsets, which are different. Add the offsets so the
mentioned platform can be fixed later on. Add the new PCS offsets
in a dedicated header file.

Fixes: d7b3579f84f7 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-2-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: qserdes-txrx: Add missing registers offsets 2024-06-03T14:00:47+00:00 Abel Vesa abel.vesa@linaro.org 2024-05-27T07:20:35+00:00 5314e84c33e7ad61df5203df540626ac59f9dcd9 Currently, the x1e80100 uses pure V6 register offsets for DP part of the combo PHY. This hasn't been an issue because external DP is not yet enabled on any of the boards yet. But in order to enabled it, all these new V6 N4 register offsets are needed. So add them. Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets") Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Currently, the x1e80100 uses pure V6 register offsets for DP part of the
combo PHY. This hasn't been an issue because external DP is not yet
enabled on any of the boards yet. But in order to enabled it, all these
new V6 N4 register offsets are needed. So add them.

Fixes: 762c3565f3c8 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp-usb: Add sc8180x USB UNIPHY 2024-06-03T13:57:46+00:00 Bjorn Andersson quic_bjorande@quicinc.com 2024-05-25T18:03:55+00:00 b279a835192834565db5025205394e3ef943fbd2 The SC8180X platform has two UNIPHY blocks, add support for these in the QMP driver. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-2-60a904392438@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The SC8180X platform has two UNIPHY blocks, add support for these in the
QMP driver.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240525-sc8180x-usb-mp-v1-2-60a904392438@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>