linux-stable.git/drivers/phy/qualcomm, branch v5.12.2 Linux kernel stable tree phy: qcom-qmp: make a const array static, makes object smaller 2021-02-06T10:03:22+00:00 Colin Ian King colin.king@canonical.com 2021-02-04T18:03:13+00:00 43851904cbd7c7bb18c84cc553b6232ace23747b Don't populate the const array cfg1_settings on the stack but instead make it static. Makes the object code smaller by 24 bytes: Before: text data bss dec hex filename 73585 20240 64 93889 16ec1 drivers/phy/qualcomm/phy-qcom-qmp.o After: text data bss dec hex filename 73465 20336 64 93865 16ea9 drivers/phy/qualcomm/phy-qcom-qmp.o (gcc version 10.2.0) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Don't populate the const array cfg1_settings on the stack but instead make
it static. Makes the object code smaller by 24 bytes:

Before:
   text	   data	    bss	    dec	    hex	filename
  73585	  20240	     64	  93889	  16ec1	drivers/phy/qualcomm/phy-qcom-qmp.o

After:
   text	   data	    bss	    dec	    hex	filename
  73465	  20336	     64	  93865	  16ea9	drivers/phy/qualcomm/phy-qcom-qmp.o

(gcc version 10.2.0)

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lore.kernel.org/r/20210204180313.108876-1-colin.king@canonical.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add support for SM8350 UFS phy 2021-02-06T09:54:58+00:00 Vinod Koul vkoul@kernel.org 2021-02-04T16:58:05+00:00 0e43fdb94a8363cfd78e8d14580ea2f5b82789a8 Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the tables for init sequences for UFS QMP phy found in  SM8350 SoC.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210204165805.62235-4-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add UFS V5 registers found in SM8350 2021-02-06T09:53:46+00:00 Vinod Koul vkoul@kernel.org 2021-02-04T16:58:04+00:00 920abc105b5de6489d61bd8c5d0d44463665ae3f Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the registers for UFS found in SM8350. The UFS phy used in SM8350
seems to have same offsets as V5 phy, although Documentation for that is
lacking.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210204165805.62235-3-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qualcomm: usb28nm: Add MDM9607 init sequence 2021-02-04T08:05:39+00:00 Konrad Dybcio konrad.dybcio@somainline.org 2021-01-31T01:31:24+00:00 557a28811c7e0286d3816842032db5eb7bb5f156 This is required to bring up the PHY on MDM9607-based boards. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
This is required to bring up the PHY on MDM9607-based boards.

Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210131013124.54484-1-konrad.dybcio@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qusb2: add QUSB2 support for IPQ6018 2021-02-04T07:50:13+00:00 Kathiravan T kathirav@codeaurora.org 2021-01-27T14:20:27+00:00 2cfbe6765b7a61feebbbcfdd4aecb6e6de38b361 Add the phy init sequence for the Super Speed ports found on IPQ6018. Signed-off-by: Kathiravan T <kathirav@codeaurora.org> [baruch: add ipq6018_regs_layout[], drop binding change] Signed-off-by: Baruch Siach <baruch@tkos.co.il> Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add the phy init sequence for the Super Speed ports found
on IPQ6018.

Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
[baruch: add ipq6018_regs_layout[], drop binding change]
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Link: https://lore.kernel.org/r/b8c22dddf1f70d89e135fe1ae705ddc68e295ebb.1611756920.git.baruch@tkos.co.il
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add SC8180X USB phy 2021-02-04T07:06:11+00:00 Bjorn Andersson bjorn.andersson@linaro.org 2021-01-21T01:43:39+00:00 4d1a6404e91efffe3192e1405e175fc7fb3fa3de The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are either the same or very similar to the same found in SM8150. Add a compatible for this, reusing the existing SM8150 USB phy config. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The Qualcomm SC8180X has two QMP phys used for SuperSpeed USB, which are
either the same or very similar to the same found in SM8150. Add a
compatible for this, reusing the existing SM8150 USB phy config.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210121014339.1612525-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add SC8180X UFS phy 2021-02-04T07:06:11+00:00 Bjorn Andersson bjorn.andersson@linaro.org 2021-01-20T22:45:31+00:00 a5a621ad0ab44aa672385e0dddc730c3e50a908f The UFS phy found in the Qualcomm SC8180X is either the same or very similar to the phy present in SM8150, so add a compatible and reuse the SM8150 configuration. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The UFS phy found in the Qualcomm SC8180X is either the same or very
similar to the phy present in SM8150, so add a compatible and reuse the
SM8150 configuration.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210120224531.1610709-2-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qusb2: Add configuration for SDM660 2021-01-19T15:07:54+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@somainline.org 2021-01-14T17:47:17+00:00 b0e7f781fc9958bfb57527a49c5a1eb1f423439c The SDM660 SoC uses the same configuration as MSM8996, but the clock scheme uses a differential reference clock and none of the SoCs in this series (630, 636 and others) have got a usable PHY_CLK_SCHEME register in the TCSR for clk scheme detection. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The SDM660 SoC uses the same configuration as MSM8996, but the
clock scheme uses a differential reference clock and none of
the SoCs in this series (630, 636 and others) have got a usable
PHY_CLK_SCHEME register in the TCSR for clk scheme detection.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114174718.398638-2-angelogioacchino.delregno@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qusb2: Allow specifying default clock scheme 2021-01-19T15:06:01+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@somainline.org 2021-01-14T17:47:16+00:00 26e6d50e93129af85a759820c1608be8b470f229 The TCSR's PHY_CLK_SCHEME register is not available on all SoC models, but some may still use a differential reference clock. In preparation for these SoCs, add a se_clk_scheme_default configuration entry and declare it to true for all currently supported SoCs (retaining the previous defaults. This patch brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The TCSR's PHY_CLK_SCHEME register is not available on all SoC
models, but some may still use a differential reference clock.

In preparation for these SoCs, add a se_clk_scheme_default
configuration entry and declare it to true for all currently
supported SoCs (retaining the previous defaults.

This patch brings no functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210114174718.398638-1-angelogioacchino.delregno@somainline.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: qcom-qmp: Add SM8350 USB QMP PHYs 2021-01-19T15:02:31+00:00 Jack Pham jackp@codeaurora.org 2021-01-15T17:47:21+00:00 10c744d48d7f01b0d0c954d8d71aebd07705a7b9 Add support for the USB DP & UNI PHYs found on SM8350. These use version 5.0.0 of the QMP PHY IP and thus require new "V5" definitions of the register offset macros for the QSERDES RX and TX blocks. The QSERDES common and QPHY PCS blocks' register offsets are largely unchanged from V4 so some of the existing macros can be reused. Signed-off-by: Jack Pham <jackp@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add support for the USB DP & UNI PHYs found on SM8350. These use
version 5.0.0 of the QMP PHY IP and thus require new "V5"
definitions of the register offset macros for the QSERDES RX
and TX blocks. The QSERDES common and QPHY PCS blocks' register
offsets are largely unchanged from V4 so some of the existing
macros can be reused.

Signed-off-by: Jack Pham <jackp@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210115174723.7424-3-jackp@codeaurora.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>