linux-stable.git/drivers/phy/qualcomm, branch v5.10

phy: qualcomm: Fix 28 nm Hi-Speed USB PHY OF dependency

2020-11-16T07:50:38+00:00

This Kconfig entry should declare a dependency on OF

Fixes: 67b27dbeac4d ("phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver")
Signed-off-by: Bryan O'Donoghue 
Link: https://lore.kernel.org/r/20201113151225.1657600-3-bryan.odonoghue@linaro.org
Signed-off-by: Vinod Koul

phy: qualcomm: usb: Fix SuperSpeed PHY OF dependency

2020-11-16T07:50:38+00:00

This Kconfig entry should declare a dependency on OF

Fixes: 6076967a500c ("phy: qualcomm: usb: Add SuperSpeed PHY driver")
Reported-by: kernel test robot 
Link: https://lkml.org/lkml/2020/11/13/414
Signed-off-by: Bryan O'Donoghue 
Link: https://lore.kernel.org/r/20201113151225.1657600-2-bryan.odonoghue@linaro.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Initialize another pointer to NULL

2020-10-28T16:17:50+00:00

This probe function is too complicated and should be refactored. For now
let's just set this variable to NULL and keep the static analysis tools
happy.

Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy")
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 
Signed-off-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20201026205942.2861828-1-swboyd@chromium.org
Signed-off-by: Vinod Koul

Merge tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into usb-next

2020-10-02T11:45:00+00:00

Vinod writes:

phy for 5.9

 - Core:
   - New PHY attribute for max_link_rate

 - New phy drivers:
   - Rockchip dphy driver moved from staging
   - Socionext UniPhier AHCI PHY driver
   - Intel LGM SoC USB phy
   - Intel Keem Bay eMMC PHY driver

 - Updates:
   - Support for imx8mp usb phy
   - Support for DP Phy and USB3+DP combo phy in QMP driver
   - Support for Qualcomm sc7180 DP phy
   - Support for cadence torrent PCIe and USB single linke and multilink
     configurations along with USB, SGMII/QSGMII configurations

* tag 'phy-for-5.10' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
  phy: qcom-qmp: initialize the pointer to NULL
  phy: qcom-qmp: Add support for sc7180 DP phy
  phy: qcom-qmp: Add support for DP in USB3+DP combo phy
  phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify
  phy: qcom-qmp: Get dp_com I/O resource by index
  phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
  phy: qcom-qmp: Remove 'initialized' in favor of 'init_count'
  phy: qcom-qmp: Move phy mode into struct qmp_phy
  dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information
  dt-bindings: phy: ti,phy-j721e-wiz: fix bindings for torrent phy
  dt-bindings: phy: cdns,torrent-phy: add reset-names
  phy: rockchip-dphy-rx0: Include linux/delay.h
  phy: fix USB_LGM_PHY warning & build errors
  phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration
  phy: cadence-torrent: Add PCIe + USB multilink configuration
  phy: cadence-torrent: Add single link USB register sequences
  phy: cadence-torrent: Add single link SGMII/QSGMII register sequences
  phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals
  phy: cadence-torrent: Add PHY link configuration sequences for single link
  phy: cadence-torrent: Add clk changes for multilink configuration
  ...

phy: qcom-qmp: initialize the pointer to NULL

2020-10-01T07:36:40+00:00

Smatch complains:
drivers/phy/qualcomm/phy-qcom-qmp.c:3899 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_cfg'.
drivers/phy/qualcomm/phy-qcom-qmp.c:3900 qcom_qmp_phy_probe() error: uninitialized symbol 'dp_serdes'.
drivers/phy/qualcomm/phy-qcom-qmp.c:3902 qcom_qmp_phy_probe() error: uninitialized symbol 'usb_cfg'.

This is a warning but not a practical one as dp_cfg, dp_serdes and
usb_cfg will be set and used when valid. So we can set the pointers to
NULL to quiesce the warnings.

Fixes: 52e013d0bffa ("phy: qcom-qmp: Add support for DP in USB3+DP combo phy")
Reported-by: kernel test robot 
Reported-by: Dan Carpenter 
Reviewed-by: Stephen Boyd 
Link: https://lore.kernel.org/r/20201001070911.140019-1-vkoul@kernel.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Add support for sc7180 DP phy

2020-09-28T05:57:53+00:00

Add the necessary compatible strings and phy data for the sc7180 USB3+DP
combo phy.

Signed-off-by: Stephen Boyd 
Cc: Jeykumar Sankaran 
Cc: Chandan Uddaraju 
Cc: Vara Reddy 
Cc: Tanmay Shah 
Cc: Bjorn Andersson 
Cc: Manu Gautam 
Cc: Sandeep Maheswaram 
Cc: Douglas Anderson 
Cc: Sean Paul 
Cc: Jonathan Marek 
Cc: Dmitry Baryshkov 
Cc: Rob Clark 
Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
Link: https://lore.kernel.org/r/20200916231202.3637932-9-swboyd@chromium.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Add support for DP in USB3+DP combo phy

2020-09-28T05:57:53+00:00

Add support for the USB3 + DisplayPort (DP) "combo" phy to the qmp phy
driver. We already have support for the USB3 part of the combo phy, so
most additions are for the DP phy.

Split up the qcom_qmp_phy{enable,disable}() functions into the phy init,
power on, power off, and exit functions that the common phy framework
expects so that the DP phy can add even more phy ops like
phy_calibrate() and phy_configure(). This allows us to initialize the DP
PHY and configure the AUX channel before powering on the PHY at the link
rate that was negotiated during link training.

The general design is as follows:

  1) DP controller calls phy_init() to initialize the PHY and configure
  the dp_com register region.

  2) DP controller calls phy_configure() to tune the link rate and
  voltage swing and pre-emphasis settings.

  3) DP controller calls phy_power_on() to enable the PLL and power on
  the phy.

  4) DP controller calls phy_configure() again to tune the voltage swing
  and pre-emphasis settings determind during link training.

  5) DP controller calls phy_calibrate() some number of times to change
  the aux settings if the aux channel times out during link training.

  6) DP controller calls phy_power_off() if the link rate is to be
  changed and goes back to step 2 to try again at a different link rate.

  5) DP controller calls phy_power_off() and then phy_exit() to power
  down the PHY when it is done.

The DP PHY contains a PLL that is different from the one used for the
USB3 PHY. Instead of a pipe clk there is a link clk and a pixel clk
output from the DP PLL after going through various dividers. Introduce
clk ops for these two clks that just tell the child clks what the
frequency of the pixel and link are. When the phy link rate is
configured we call clk_set_rate() to update the child clks in the
display clk controller on what rate is in use. The clk frequencies
always differ based on the link rate (i.e. 1.6Gb/s 2.7Gb/s, 5.4Gb/s, or
8.1Gb/s corresponding to various transmission modes like HBR1, HBR2 or
HBR3) so we simply store the link rate and use that to calculate the clk
frequencies.

The PLL enable sequence is a little different from other QMP phy PLLs so
we power on the PLL in qcom_qmp_phy_configure_dp_phy() that gets called
from phy_power_on(). This should probably be split out better so that
each phy has a way to run the final PLL/PHY enable sequence.

This code is based on a submission of this phy and PLL in the drm
subsystem.

Signed-off-by: Stephen Boyd 
Cc: Jeykumar Sankaran 
Cc: Chandan Uddaraju 
Cc: Vara Reddy 
Cc: Tanmay Shah 
Cc: Bjorn Andersson 
Cc: Manu Gautam 
Cc: Sandeep Maheswaram 
Cc: Douglas Anderson 
Cc: Sean Paul 
Cc: Stephen Boyd 
Cc: Jonathan Marek 
Cc: Dmitry Baryshkov 
Cc: Rob Clark 
Link: https://lore.kernel.org/r/20200609034623.10844-1-tanmay@codeaurora.org
Link: https://lore.kernel.org/r/20200916231202.3637932-8-swboyd@chromium.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify

2020-09-28T05:57:53+00:00

We can use the wrapper API here to save some lines and remove the need
for the 'base' and 'res' local variable.

Suggested-by: Bjorn Andersson 
Signed-off-by: Stephen Boyd 
Cc: Jeykumar Sankaran 
Cc: Chandan Uddaraju 
Cc: Vara Reddy 
Cc: Tanmay Shah 
Cc: Bjorn Andersson 
Cc: Manu Gautam 
Cc: Sandeep Maheswaram 
Cc: Douglas Anderson 
Cc: Sean Paul 
Cc: Jonathan Marek 
Cc: Dmitry Baryshkov 
Cc: Rob Clark 
Link: https://lore.kernel.org/r/20200916231202.3637932-7-swboyd@chromium.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Get dp_com I/O resource by index

2020-09-28T05:57:53+00:00

The dp_com resource is always at index 1 according to the dts files in
the kernel. Get this resource by index so that we don't need to make
future additions to the DT binding use 'reg-names'.

Signed-off-by: Stephen Boyd 
Cc: Jeykumar Sankaran 
Cc: Chandan Uddaraju 
Cc: Vara Reddy 
Cc: Tanmay Shah 
Cc: Bjorn Andersson 
Cc: Manu Gautam 
Cc: Sandeep Maheswaram 
Cc: Douglas Anderson 
Cc: Sean Paul 
Cc: Jonathan Marek 
Cc: Dmitry Baryshkov 
Cc: Rob Clark 
Link: https://lore.kernel.org/r/20200916231202.3637932-6-swboyd@chromium.org
Signed-off-by: Vinod Koul

phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'

2020-09-28T05:57:53+00:00

The serdes I/O region is where the PLL for the phy is controlled.
Sometimes the PLL is shared between multiple phys, for example in the
PCIe case where there are three phys inside the same wrapper. Other
times the PLL is for a single phy, i.e. some USB3 phys. To complete the
trifecta we have the USB3+DP combo phy where the USB3 and DP phys each
have their own serdes region because they have their own PLL while they
both share a common I/O region pertaining to the USB type-c pinout and
cable orientation.

Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can
correlate PLL control to the phy that uses it. This allows us to support
the USB3+DP combo phy in this driver. This isn't a problem for the
3-lane/phy PCIe phy because there is a common init function that is the
only place the serdes region is programmed.

Furthermore, move the configuration data that contains most of the
register programming sequences to the qmp phy struct. This data isn't
qmp wrapper specific. It is phy specific data used to tune various
settings for things like pre-emphasis, bias, etc.

Signed-off-by: Stephen Boyd 
Cc: Jeykumar Sankaran 
Cc: Chandan Uddaraju 
Cc: Vara Reddy 
Cc: Tanmay Shah 
Cc: Bjorn Andersson 
Cc: Manu Gautam 
Cc: Sandeep Maheswaram 
Cc: Douglas Anderson 
Cc: Sean Paul 
Cc: Jonathan Marek 
Cc: Dmitry Baryshkov 
Cc: Rob Clark 
Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org
Signed-off-by: Vinod Koul