linux-stable.git/drivers/phy/freescale, branch v6.4

phy: freescale: phy-fsl-imx8qm-lvds-phy: Convert to platform remove callback returning void

2023-03-20T12:44:56+00:00

The .remove() callback for a platform driver returns an int which makes
many driver authors wrongly assume it's possible to do error handling by
returning an error code. However the value returned is (mostly) ignored
and this typically results in resource leaks. To improve here there is a
quest to make the remove callback return void. In the first step of this
quest all drivers are converted to .remove_new() which already returns
void.

Trivially convert this driver from always returning zero in the remove
callback to the void returning variant.

Signed-off-by: Uwe Kleine-König 
Link: https://lore.kernel.org/r/20230307115900.2293120-7-u.kleine-koenig@pengutronix.de
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Add one missing error return

2023-01-13T17:55:38+00:00

There should be one error return when fail to fetch the perst reset.
Add the missing error return.

Fixes: dce9edff16ee ("phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support")

Signed-off-by: Richard Zhu 
Reviewed-by: Marek Vasut 
Link: https://lore.kernel.org/r/1671433941-2037-1-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Add i.MX8MP PCIe PHY support

2022-10-17T05:31:03+00:00

Add i.MX8MP PCIe PHY support.

Signed-off-by: Richard Zhu 
Signed-off-by: Lucas Stach 
Tested-by: Marek Vasut 
Tested-by: Richard Leitner 
Tested-by: Alexander Stein 
Reviewed-by: Lucas Stach 
Reviewed-by: Ahmad Fatoum 
Link: https://lore.kernel.org/r/1665625622-20551-5-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver

2022-10-17T05:31:02+00:00

To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY
driver.
- Use gpr compatible string to avoid the codes duplications when add
  another platform PCIe PHY support.
- Re-arrange the codes to let it more flexible and easy to expand.
No functional change. Re-arrange the TX tuning, since internal registers
can be wrote through APB interface before assertion of CMN_RST.

Signed-off-by: Richard Zhu 
Signed-off-by: Lucas Stach 
Tested-by: Marek Vasut 
Tested-by: Richard Leitner 
Tested-by: Alexander Stein 
Reviewed-by: Lucas Stach 
Reviewed-by: Ahmad Fatoum 
Link: https://lore.kernel.org/r/1665625622-20551-4-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Refine register definitions

2022-10-17T05:31:02+00:00

No function changes, refine PHY register definitions.
- Keep align with other CMN PHY registers, refine the definitions of
  PHY_CMN_REG75.
- Remove two BIT definitions that are not used at all.

Signed-off-by: Richard Zhu 
Signed-off-by: Lucas Stach 
Tested-by: Marek Vasut 
Tested-by: Richard Leitner 
Tested-by: Alexander Stein 
Reviewed-by: Lucas Stach 
Link: https://lore.kernel.org/r/1665625622-20551-3-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()

2022-10-03T08:34:46+00:00

Refer to phy_core driver, phy_init() must be called before phy_power_on().
Fix the wrong order of phy_init() and phy_power_on() here.

Link: https://lore.kernel.org/r/1662344583-18874-1-git-send-email-hongxing.zhu@nxp.com
Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
Tested-by: Alexander Stein 
Signed-off-by: Richard Zhu 
Signed-off-by: Lorenzo Pieralisi 
Acked-by: Vinod Koul 
Acked-by: Lorenzo Pieralisi

phy: freescale: Add i.MX8qm Mixel LVDS PHY support

2022-07-08T05:13:20+00:00

Add Freescale i.MX8qm LVDS PHY support.
The PHY IP is from Mixel, Inc.

Signed-off-by: Liu Ying 
Link: https://lore.kernel.org/r/20220706034810.2352641-4-victor.liu@nxp.com
Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED

2022-04-20T09:15:55+00:00

The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.

The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.

Reviewed-by: Richard Zhu 
Signed-off-by: Marek Vasut 
Cc: Fabio Estevam 
Cc: Kishon Vijay Abraham I 
Cc: Marcel Ziswiler 
Cc: NXP Linux Team 
Cc: Peng Fan 
Cc: Richard Zhu 
Cc: Shawn Guo 
Cc: Vinod Koul 
Cc: linux-arm-kernel@lists.infradead.org
To: linux-phy@lists.infradead.org
Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de
Signed-off-by: Vinod Koul

phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support

2022-04-20T07:29:50+00:00

i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports
either a MIPI DSI display or a LVDS display.  The PHY mode is controlled
by SCU firmware and the driver would call a SCU firmware function to
configure the PHY mode.  The single LVDS PHY has 4 data lanes to support
a LVDS display.  Also, with a master LVDS PHY and a slave LVDS PHY, they
may work together to support a LVDS display with 8 data lanes(usually, dual
LVDS link display).  Note that this patch supports the LVDS PHY mode only
for the i.MX8qxp Mixel combo PHY, i.e., the MIPI DPHY mode is yet to be
supported, so for now error would be returned from ->set_mode() if MIPI
DPHY mode is passed over to it for the combo PHY.

Cc: Guido Günther 
Cc: Robert Chiras 
Cc: Kishon Vijay Abraham I 
Cc: Vinod Koul 
Cc: Shawn Guo 
Cc: Sascha Hauer 
Cc: Pengutronix Kernel Team 
Cc: Fabio Estevam 
Cc: NXP Linux Team 
Reviewed-by: Guido Günther 
Signed-off-by: Liu Ying 
Link: https://lore.kernel.org/r/20220419010852.452169-6-victor.liu@nxp.com
Signed-off-by: Vinod Koul

phy: PHY_FSL_LYNX_28G should depend on ARCH_LAYERSCAPE

2022-03-29T15:45:16+00:00

Freescale Layerscape Lynx 28G SerDes PHYs are only present on
Freescale/NXP Layerscape SoCs.

Move PHY_FSL_LYNX_28G outside the block for ARCH_MXC, as the latter
is meant for i.MX8 SoCs, which is a different family than Layerscape.
Add a dependency on ARCH_LAYERSCAPE, to prevent asking the user about
this driver when configuring a kernel without Layerscape SoC support.

Fixes: 02e2af20f4f9f2aa ("Merge tag 'char-misc-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc")
Fixes: 8f73b37cf3fbda67 ("phy: add support for the Layerscape SerDes 28G")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Linus Torvalds