linux-stable.git/drivers/phy/cadence, branch linux-5.7.y Linux kernel stable tree phy: cadence: sierra: Fix for USB3 U1/U2 state 2020-06-24T15:48:48+00:00 Sanket Parmar sparmar@cadence.com 2020-05-18T12:14:13+00:00 8f484bf25475d4ce18e87d256511e7ff11dc2c2e [ Upstream commit 2bcf14ca1a2f3202954f812f380c7fa8127fbd7f ] Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 2bcf14ca1a2f3202954f812f380c7fa8127fbd7f ]

Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.

Signed-off-by: Sanket Parmar <sparmar@cadence.com>
Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com
Reviewed-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
phy: cadence-torrent: Add support for subnode bindings 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:11:01+00:00 afa4ba059f1e9884f9edad2545a71b7373ff1be0 Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Implement single link subnode support to the phy driver.
Add reset support including PHY reset and individual lane reset.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Add platform dependent initialization structure 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:11:00+00:00 597bf3f1a611517e70a62093f5b68cba45622f9b Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add platform dependent initialization data for Torrent PHY used in TI's
J721E SoC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Use regmap to read and write DPTX PHY registers 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:59+00:00 cba472ecdb58b8363c73c6ae2404194be48f9aec Use regmap to read and write DPTX specific PHY registers. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Use regmap to read and write DPTX specific PHY registers.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Use regmap to read and write Torrent PHY registers 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:58+00:00 69d114acd6541c6642f08decda38484f3d5a0bf7 Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Use regmap for accessing Torrent PHY registers. Modify register offsets
as defined in Torrent PHY user guide. Abstract address calculation
using regmap APIs.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Implement PHY configure APIs 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:57+00:00 572d659256eb44ddd153e77f904cb3e5bc995f40 Add support for PHY configuration APIs. These will mainly reconfigure link rate, number of lanes, voltage swing and pre-emphasis values. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add support for PHY configuration APIs. These will mainly reconfigure
link rate, number of lanes, voltage swing and pre-emphasis values.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Add 19.2 MHz reference clock support 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:56+00:00 e4b496a376f1ad83d708628e31e90c4e1093a867 Add configuration functions for 19.2 MHz refclock support. Add register configurations for SSC support. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add configuration functions for 19.2 MHz refclock support.
Add register configurations for SSC support.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Refactor code for reusability 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:55+00:00 21c79146a1bbc6310dc7dcf085c5ab5b0a553fcb Add a separate function to set different power state values. Use uniform polling timeout value. Also check return values of functions for proper error handling. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add a separate function to set different power state values.
Use uniform polling timeout value. Also check return values
of functions for proper error handling.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Add wrapper for DPTX register access 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:54+00:00 f61b3aed20003ec27960dde50ceaea04479d1f07 Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add wrapper functions to read, write DisplayPort specific PHY registers to
improve code readability.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
phy: cadence-torrent: Add wrapper for PHY register access 2020-03-20T14:04:29+00:00 Swapnil Jakhade sjakhade@cadence.com 2020-02-06T06:10:53+00:00 ccb1b89de37efeee74b46b8bd0bf632be92a7c08 Add a wrapper function to write Torrent PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by: Yuti Amonkar <yamonkar@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> 
Add a wrapper function to write Torrent PHY registers to improve
code readability.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Yuti Amonkar <yamonkar@cadence.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>