linux-stable.git/drivers/phy/allwinner, branch linux-6.3.y

phy: sun4i-usb: Replace types with explicit quirk flags

2023-01-12T17:38:57+00:00

So far we were assigning some crude "type" (SoC name, really) to each
Allwinner USB PHY model, then guarding certain quirks based on this.
This does not only look weird, but gets more or more cumbersome to
maintain.

Remove the bogus type names altogether, instead introduce flags for each
quirk, and explicitly check for them.
This improves readability, and simplifies future extensions.

Signed-off-by: Andre Przywara 
Reviewed-by: Jernej Skrabec 
Link: https://lore.kernel.org/r/20230109012223.4079299-4-andre.przywara@arm.com
Signed-off-by: Vinod Koul

phy: sun4i-usb: add support for the USB PHY on F1C100s SoC

2023-01-12T17:38:57+00:00

The F1C100s SoC has one USB OTG port connected to a MUSB controller.

Add support for its USB PHY.

Signed-off-by: Icenowy Zheng 
Acked-by: Jernej Skrabec 
Signed-off-by: Andre Przywara 
Link: https://lore.kernel.org/r/20230109012223.4079299-3-andre.przywara@arm.com
Signed-off-by: Vinod Koul

phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant

2022-11-24T17:34:24+00:00

A100 features an updated DPHY, which moves PLL control inside the DPHY
register space (previously the PLL was controlled from the CCU). It also
requires a modified analog power-on sequence. This "combo PHY" can also
be used as an LVDS PHY, but that is not yet supported by the driver.

Signed-off-by: Samuel Holland 
Link: https://lore.kernel.org/r/20221114022113.31694-9-samuel@sholland.org
Signed-off-by: Vinod Koul

phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook

2022-11-24T17:34:24+00:00

The A100 variant uses the same values for the timing registers, and it
uses the same final power-on sequence, but it needs a different analog
register configuration in the middle. Support this by moving the
variant-specific parts to a hook provided by the variant.

Signed-off-by: Samuel Holland 
Link: https://lore.kernel.org/r/20221114022113.31694-8-samuel@sholland.org
Signed-off-by: Vinod Koul

phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last

2022-11-24T17:34:23+00:00

The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.

Reviewed-by: Paul Kocialkowski 
Signed-off-by: Samuel Holland 
Link: https://lore.kernel.org/r/20221114022113.31694-7-samuel@sholland.org
Signed-off-by: Vinod Koul

phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional

2022-11-24T17:34:23+00:00

While all variants of the DPHY likely support RX mode, the new variant
in the A100 is not used in this direction by the BSP, and it has some
analog register changes, so its RX power-on sequence is unknown. To be
safe, limit RX support to variants where the power-on sequence is known.

Signed-off-by: Samuel Holland 
Link: https://lore.kernel.org/r/20221114022113.31694-6-samuel@sholland.org
Signed-off-by: Vinod Koul

phy: sun4i-usb: Add support for the H616 USB PHY

2022-11-07T04:50:25+00:00

The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and puts SIDDQ on a different bit like
the A100. Plus it needs this weird PHY2 quirk.

Name all those properties in a new config struct and assign a new
compatible name to it.

Signed-off-by: Andre Przywara 
Reviewed-by: Samuel Holland 
Link: https://lore.kernel.org/r/20221031111358.3387297-5-andre.przywara@arm.com
Signed-off-by: Vinod Koul

phy: sun4i-usb: Introduce port2 SIDDQ quirk

2022-11-07T04:50:25+00:00

At least the Allwinner H616 SoC requires a weird quirk to make most
USB PHYs work: Only port2 works out of the box, but all other ports
need some help from this port2 to work correctly: The CLK_BUS_PHY2 and
RST_USB_PHY2 clock and reset need to be enabled, and the SIDDQ bit in
the PMU PHY control register needs to be cleared. For this register to
be accessible, CLK_BUS_ECHI2 needs to be ungated. Don't ask ....

Instead of disguising this as some generic feature, treat it more like
a quirk (what it really is):
If the quirk bit is set, and we initialise a PHY other than PHY2, ungate
this one special clock, and clear the SIDDQ bit. We also pick the clock
and reset from PHY2 and enable them as well.

Signed-off-by: Andre Przywara 
Link: https://lore.kernel.org/r/20221031111358.3387297-4-andre.przywara@arm.com
Signed-off-by: Vinod Koul

phy: move from strlcpy with unused retval to strscpy

2022-08-30T07:42:38+00:00

Follow the advice of the below link and prefer 'strscpy' in this
subsystem. Conversion is 1:1 because the return value is not used.
Generated by a coccinelle script.

Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/
Signed-off-by: Wolfram Sang 
Acked-by: Jernej Skrabec 
Link: https://lore.kernel.org/r/20220818210056.7205-1-wsa+renesas@sang-engineering.com
Signed-off-by: Vinod Koul

phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2

2022-04-20T09:10:12+00:00

The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.

This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.

It uses the direction dt property to distinguish between tx and rx
directions.

Signed-off-by: Paul Kocialkowski 
Link: https://lore.kernel.org/r/20220415152138.635525-3-paul.kocialkowski@bootlin.com
Signed-off-by: Vinod Koul