linux-stable.git/drivers/pci/controller, branch v5.1.2 Linux kernel stable tree Merge tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci 2019-03-09T22:57:08+00:00 Linus Torvalds torvalds@linux-foundation.org 2019-03-09T22:57:08+00:00 2901752c14b8e1b7dd898d2e5245c93e531aa624 Pull PCI updates from Bjorn Helgaas: - Use match_string() instead of reimplementing it (Andy Shevchenko) - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada) - Use Latency Tolerance Reporting if already enabled by platform (Bjorn Helgaas) - Save/restore LTR info for suspend/resume (Bjorn Helgaas) - Fix DPC use of uninitialized data (Dongdong Liu) - Probe bridge window attributes only once at enumeration-time to fix device accesses during rescan (Bjorn Helgaas) - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du Changbin) - Use config header type (not class code) identify bridges more reliably (Honghui Zhang) - Work around Intel Denverton incorrect Trace Hub BAR size reporting (Alexander Shishkin) - Reorder pciehp cached state/hardware state updates to avoid missed interrupts (Mika Westerberg) - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann) - Mark expected switch fall-through (Mathieu Malaterre) - Use of_node_name_eq() for node name comparisons (Rob Herring) - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang) - Consolidate Rohm Vendor ID definitions (Andy Shevchenko) - Use u32 (not __u32) for things not exposed to userspace (Logan Gunthorpe) - Fix locking semantics of bus and slot reset interfaces (Alex Williamson) - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang) - Allow portdrv to claim subtractive decode Ports so PCIe services will work for them (Honghui Zhang) - Report PCIe links that become degraded at run-time (Alexandru Gagniuc) - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt hotplug (Mika Westerberg) - Revert runtime PM suspend/resume callbacks that broke PME on network cable plug (Mika Westerberg) - Disable Data Link State Changed interrupts to prevent wakeup immediately after suspend (Mika Westerberg) - Extend altera to support Stratix 10 (Ley Foon Tan) - Allow building altera driver on ARM64 (Ley Foon Tan) - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint maintainer (Lorenzo Pieralisi) - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro) - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) - Configure MPS settings for VMD root ports (Jon Derrick) * tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits) PCI: Update PCIEPORTBUS Kconfig help text PCI: Fix "try" semantics of bus and slot reset PCI/LINK: Report degraded links via link bandwidth notification dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0 PCI: altera: Enable driver on ARM64 PCI: altera: Add Stratix 10 PCIe support PCI/PME: Fix possible use-after-free on remove PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ ... 
Pull PCI updates from Bjorn Helgaas:

 - Use match_string() instead of reimplementing it (Andy Shevchenko)

 - Enable SERR# forwarding for all bridges (Bharat Kumar Gogada)

 - Use Latency Tolerance Reporting if already enabled by platform (Bjorn
   Helgaas)

 - Save/restore LTR info for suspend/resume (Bjorn Helgaas)

 - Fix DPC use of uninitialized data (Dongdong Liu)

 - Probe bridge window attributes only once at enumeration-time to fix
   device accesses during rescan (Bjorn Helgaas)

 - Return BAR size (not "size -1 ") from pci_size() to simplify code (Du
   Changbin)

 - Use config header type (not class code) identify bridges more
   reliably (Honghui Zhang)

 - Work around Intel Denverton incorrect Trace Hub BAR size reporting
   (Alexander Shishkin)

 - Reorder pciehp cached state/hardware state updates to avoid missed
   interrupts (Mika Westerberg)

 - Turn ibmphp semaphores into completions or mutexes (Arnd Bergmann)

 - Mark expected switch fall-through (Mathieu Malaterre)

 - Use of_node_name_eq() for node name comparisons (Rob Herring)

 - Add ACS and pciehp quirks for HXT SD4800 (Shunyong Yang)

 - Consolidate Rohm Vendor ID definitions (Andy Shevchenko)

 - Use u32 (not __u32) for things not exposed to userspace (Logan
   Gunthorpe)

 - Fix locking semantics of bus and slot reset interfaces (Alex
   Williamson)

 - Update PCIEPORTBUS Kconfig help text (Hou Zhiqiang)

 - Allow portdrv to claim subtractive decode Ports so PCIe services will
   work for them (Honghui Zhang)

 - Report PCIe links that become degraded at run-time (Alexandru
   Gagniuc)

 - Blacklist Gigabyte X299 Root Port power management to fix Thunderbolt
   hotplug (Mika Westerberg)

 - Revert runtime PM suspend/resume callbacks that broke PME on network
   cable plug (Mika Westerberg)

 - Disable Data Link State Changed interrupts to prevent wakeup
   immediately after suspend (Mika Westerberg)

 - Extend altera to support Stratix 10 (Ley Foon Tan)

 - Allow building altera driver on ARM64 (Ley Foon Tan)

 - Replace Douglas with Tom Joseph as Cadence PCI host/endpoint
   maintainer (Lorenzo Pieralisi)

 - Add DT support for R-Car RZ/G2E (R8A774C0) (Fabrizio Castro)

 - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I)

 - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay
   Abraham I)

 - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I)

 - Simplify dwc (remove unnecessary header includes, name variables
   consistently, reduce inverted logic, etc) (Gustavo Pimentel)

 - Add i.MX8MQ support (Andrey Smirnov)

 - Add message to help debug dwc MSI-X mask bit errors (Gustavo
   Pimentel)

 - Work around imx7d PCIe PLL erratum (Trent Piepho)

 - Don't assert qcom reset GPIO during probe (Bjorn Andersson)

 - Skip dwc MSI init if MSIs have been disabled (Lucas Stach)

 - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
   endpoint framework (Wen Yang)

 - Add interface to discover supported endpoint features to replace a
   bitfield that wasn't flexible enough (Kishon Vijay Abraham I)

 - Implement the new supported-feature interface for designware-plat,
   dra7xx, rockchip, cadence (Kishon Vijay Abraham I)

 - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)

 - Add layerscape endpoint mode support (Xiaowei Bao)

 - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya
   Nakamura)

 - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of
   open-coded reimplementation (Maya Nakamura)

 - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura)

 - Fix mediatek MMIO size computation to enable full size of available
   MMIO space (Honghui Zhang)

 - Fix mediatek DMA window size computation to allow endpoint DMA access
   to full DRAM address range (Honghui Zhang)

 - Fix mvebu prefetchable BAR regression caused by common bridge
   emulation that assumed all bridges had prefetchable windows (Thomas
   Petazzoni)

 - Make advk_pci_bridge_emul_ops static (Wei Yongjun)

 - Configure MPS settings for VMD root ports (Jon Derrick)

* tag 'pci-v5.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (92 commits)
  PCI: Update PCIEPORTBUS Kconfig help text
  PCI: Fix "try" semantics of bus and slot reset
  PCI/LINK: Report degraded links via link bandwidth notification
  dt-bindings: PCI: altera: Add altr,pcie-root-port-2.0
  PCI: altera: Enable driver on ARM64
  PCI: altera: Add Stratix 10 PCIe support
  PCI/PME: Fix possible use-after-free on remove
  PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static
  PCI: dwc: skip MSI init if MSIs have been explicitly disabled
  PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset()
  PCI: hv: Replace hv_vp_set with hv_vpset
  PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt
  PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
  PCI: mediatek: Fix memory mapped IO range size computation
  PCI: dwc: Remove superfluous shifting in definitions
  PCI: dwc: Make use of GENMASK/FIELD_PREP
  PCI: dwc: Make use of BIT() in constant definitions
  PCI: dwc: Share code for dw_pcie_rd/wr_other_conf()
  PCI: dwc: Make use of IS_ALIGNED()
  PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ
  ...
Merge branch 'remotes/lorenzo/pci/vmd' 2019-03-06T21:30:24+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:24+00:00 dd92b6677e3d0d78e261a7f00f28e753bab41d24 - Configure MPS settings for VMD root ports (Jon Derrick) * remotes/lorenzo/pci/vmd: PCI/VMD: Configure MPS settings before adding devices 
  - Configure MPS settings for VMD root ports (Jon Derrick)

* remotes/lorenzo/pci/vmd:
  PCI/VMD: Configure MPS settings before adding devices
Merge branch 'remotes/lorenzo/pci/misc' 2019-03-06T21:30:23+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:23+00:00 5b90fc562cbc59cef10689ab0716c724d927c600 - Fix mvebu prefetchable BAR regression caused by common bridge emulation that assumed all bridges had prefetchable windows (Thomas Petazzoni) - Make advk_pci_bridge_emul_ops static (Wei Yongjun) * remotes/lorenzo/pci/misc: PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static PCI: pci-bridge-emul: Extend pci_bridge_emul_init() with flags PCI: pci-bridge-emul: Create per-bridge copy of register behavior 
  - Fix mvebu prefetchable BAR regression caused by common bridge emulation
    that assumed all bridges had prefetchable windows (Thomas Petazzoni)

  - Make advk_pci_bridge_emul_ops static (Wei Yongjun)

* remotes/lorenzo/pci/misc:
  PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static
  PCI: pci-bridge-emul: Extend pci_bridge_emul_init() with flags
  PCI: pci-bridge-emul: Create per-bridge copy of register behavior
Merge branch 'remotes/lorenzo/pci/mediatek' 2019-03-06T21:30:23+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:23+00:00 d00aaa88c33a9df2ce72a1cffd940c2338801046 - Fix mediatek MMIO size computation to enable full size of available MMIO space (Honghui Zhang) - Fix mediatek DMA window size computation to allow endpoint DMA access to full DRAM address range (Honghui Zhang) * remotes/lorenzo/pci/mediatek: PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM PCI: mediatek: Fix memory mapped IO range size computation 
  - Fix mediatek MMIO size computation to enable full size of available
    MMIO space (Honghui Zhang)

  - Fix mediatek DMA window size computation to allow endpoint DMA access
    to full DRAM address range (Honghui Zhang)

* remotes/lorenzo/pci/mediatek:
  PCI: mediatek: Enlarge PCIe2AHB window size to support 4GB DRAM
  PCI: mediatek: Fix memory mapped IO range size computation
Merge branch 'remotes/lorenzo/pci/hv' 2019-03-06T21:30:22+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:22+00:00 a8e04a7a7f547f46089c517b664138c89a11c0f2 - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya Nakamura) - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded reimplementation (Maya Nakamura) - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura) * remotes/lorenzo/pci/hv: PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset() PCI: hv: Replace hv_vp_set with hv_vpset PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt 
  - Remove duplicate struct hv_vp_set in favor of struct hv_vpset (Maya
    Nakamura)

  - Rework hv_irq_unmask() to use cpumask_to_vpset() instead of open-coded
    reimplementation (Maya Nakamura)

  - Align Hyper-V struct retarget_msi_interrupt arguments (Maya Nakamura)

* remotes/lorenzo/pci/hv:
  PCI: hv: Refactor hv_irq_unmask() to use cpumask_to_vpset()
  PCI: hv: Replace hv_vp_set with hv_vpset
  PCI: hv: Add __aligned(8) to struct retarget_msi_interrupt
Merge branch 'remotes/lorenzo/pci/endpoint' 2019-03-06T21:30:21+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:21+00:00 7e5b22ddb2d400ace448483fa46323a6072ceca0 - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) * remotes/lorenzo/pci/endpoint: misc: pci_endpoint_test: Add the layerscape EP device support PCI: layerscape: Add EP mode support arm64: dts: Add the PCIE EP node in dts dt-bindings: add DT binding for the layerscape PCIe controller with EP mode PCI: endpoint: Remove features member in struct pci_epc PCI: designware-plat: Remove setting epc->features in Designware plat EP driver PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit PCI: pci-epf-test: Remove setting epf_bar flags in function driver PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags PCI: endpoint: Add helper to get first unreserved BAR PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops PCI: endpoint: Add new pci_epc_ops to get EPC features PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio() 
  - Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI
    endpoint framework (Wen Yang)

  - Add interface to discover supported endpoint features to replace a
    bitfield that wasn't flexible enough (Kishon Vijay Abraham I)

  - Implement the new supported-feature interface for designware-plat,
    dra7xx, rockchip, cadence (Kishon Vijay Abraham I)

  - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I)

  - Add layerscape endpoint mode support (Xiaowei Bao)

* remotes/lorenzo/pci/endpoint:
  misc: pci_endpoint_test: Add the layerscape EP device support
  PCI: layerscape: Add EP mode support
  arm64: dts: Add the PCIE EP node in dts
  dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
  PCI: endpoint: Remove features member in struct pci_epc
  PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
  PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
  PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
  PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
  PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
  PCI: pci-epf-test: Remove setting epf_bar flags in function driver
  PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
  PCI: endpoint: Add helper to get first unreserved BAR
  PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
  PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
  PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
  PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
  PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
  PCI: endpoint: Add new pci_epc_ops to get EPC features
  PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
Merge branch 'remotes/lorenzo/pci/dwc' 2019-03-06T21:30:19+00:00 Bjorn Helgaas bhelgaas@google.com 2019-03-06T21:30:19+00:00 2506419e06d4fda627376631e2619dec61b60968 - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay Abraham I) - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay Abraham I) - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I) - Simplify dwc (remove unnecessary header includes, name variables consistently, reduce inverted logic, etc) (Gustavo Pimentel) - Add i.MX8MQ support (Andrey Smirnov) - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel) - Work around imx7d PCIe PLL erratum (Trent Piepho) - Don't assert qcom reset GPIO during probe (Bjorn Andersson) - Skip dwc MSI init if MSIs have been disabled (Lucas Stach) * remotes/lorenzo/pci/dwc: PCI: dwc: skip MSI init if MSIs have been explicitly disabled PCI: dwc: Remove superfluous shifting in definitions PCI: dwc: Make use of GENMASK/FIELD_PREP PCI: dwc: Make use of BIT() in constant definitions PCI: dwc: Share code for dw_pcie_rd/wr_other_conf() PCI: dwc: Make use of IS_ALIGNED() PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ dt-bindings: imx6q-pcie: Add "pcie_aux" clock for imx8mq PCI: qcom: Don't deassert reset GPIO during probe PCI: imx: Add workaround for e10728, IMX7d PCIe PLL failure ARM: dts: imx7d: Add node for PCIe PHY dt-bindings: imx6q-pcie: Add description of imx7d pcie phy PCI: dwc: Print debug error message when MSI-X entry control mask bit is set PCI: imx6: Add support for i.MX8MQ PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag PCI: imx6: Mark PHY functions as i.MX6 specific PCI: imx6: Introduce drvdata PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit) PCI: dwc: Improve code readability and simplify mask/unmask operations PCI: dwc: Rename variable name from data to d on dw_pcie_irq_domain_free() PCI: dwc: Rename variable name from data to d on dw_pci_msi_set_affinity() PCI: dwc: Rename variable name from data to d on dw_pci_setup_msi_msg() PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask() PCI: dwc: Remove unnecessary header include (signal.h) PCI: dwc: Remove unnecessary header include (of_gpio.h) PCI: dwc: dra7xx: Invoke phy_set_mode() API to set PHY mode to PHY_MODE_PCIE PCI: dwc: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7 dt-bindings: PCI: dra7xx: Add SoC specific compatible strings 
  - Add dra72x/dra74x/dra76x SoC compatible strings (Kishon Vijay
    Abraham I)

  - Enable x2 mode support for dra72x/dra74x/dra76x SoC (Kishon Vijay
    Abraham I)

  - Configure dra7xx PHY to PCIe mode (Kishon Vijay Abraham I)

  - Simplify dwc (remove unnecessary header includes, name variables
    consistently, reduce inverted logic, etc) (Gustavo Pimentel)

  - Add i.MX8MQ support (Andrey Smirnov)

  - Add message to help debug dwc MSI-X mask bit errors (Gustavo Pimentel)

  - Work around imx7d PCIe PLL erratum (Trent Piepho)

  - Don't assert qcom reset GPIO during probe (Bjorn Andersson)

  - Skip dwc MSI init if MSIs have been disabled (Lucas Stach)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: skip MSI init if MSIs have been explicitly disabled
  PCI: dwc: Remove superfluous shifting in definitions
  PCI: dwc: Make use of GENMASK/FIELD_PREP
  PCI: dwc: Make use of BIT() in constant definitions
  PCI: dwc: Share code for dw_pcie_rd/wr_other_conf()
  PCI: dwc: Make use of IS_ALIGNED()
  PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ
  dt-bindings: imx6q-pcie: Add "pcie_aux" clock for imx8mq
  PCI: qcom: Don't deassert reset GPIO during probe
  PCI: imx: Add workaround for e10728, IMX7d PCIe PLL failure
  ARM: dts: imx7d: Add node for PCIe PHY
  dt-bindings: imx6q-pcie: Add description of imx7d pcie phy
  PCI: dwc: Print debug error message when MSI-X entry control mask bit is set
  PCI: imx6: Add support for i.MX8MQ
  PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flag
  PCI: imx6: Mark PHY functions as i.MX6 specific
  PCI: imx6: Introduce drvdata
  PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit)
  PCI: dwc: Improve code readability and simplify mask/unmask operations
  PCI: dwc: Rename variable name from data to d on dw_pcie_irq_domain_free()
  PCI: dwc: Rename variable name from data to d on dw_pci_msi_set_affinity()
  PCI: dwc: Rename variable name from data to d on dw_pci_setup_msi_msg()
  PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask()
  PCI: dwc: Remove unnecessary header include (signal.h)
  PCI: dwc: Remove unnecessary header include (of_gpio.h)
  PCI: dwc: dra7xx: Invoke phy_set_mode() API to set PHY mode to PHY_MODE_PCIE
  PCI: dwc: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72x
  dt-bindings: PCI: dra7xx: Add properties to enable x2 lane in dra7
  dt-bindings: PCI: dra7xx: Add SoC specific compatible strings
PCI: altera: Enable driver on ARM64 2019-03-04T12:22:19+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-02-28T10:52:51+00:00 5fd831cd16772188c3dd0ed9bb96418d883b4a51 Enable PCIE_ALTERA on ARM64 platform. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 
Enable PCIE_ALTERA on ARM64 platform.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
PCI: altera: Add Stratix 10 PCIe support 2019-03-04T12:22:03+00:00 Ley Foon Tan ley.foon.tan@intel.com 2019-02-28T10:52:50+00:00 49fdbd7cfece4181b711f02b7f30fd2792700382 Add PCIe Root Port support for Stratix 10 device. Main differences compared to the PCIe Root Port IP on Cyclone V and Arria 10 devices: - HIP interface to access Root Port configuration register - TLP programming flow: - One REG0 register - Don't need to check alignment Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 
Add PCIe Root Port support for Stratix 10 device.

Main differences compared to the PCIe Root Port IP on Cyclone V
and Arria 10 devices:

- HIP interface to access Root Port configuration register
- TLP programming flow:
  - One REG0 register
  - Don't need to check alignment

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
PCI: aardvark: Make symbol 'advk_pci_bridge_emul_ops' static 2019-03-01T15:23:06+00:00 Wei Yongjun weiyongjun1@huawei.com 2019-03-01T06:58:09+00:00 d3b34d048b7c1a4aac9f2e2e6ff6b0e21e50719e Fix the following sparse warning: drivers/pci/controller/pci-aardvark.c:469:28: warning: symbol 'advk_pci_bridge_emul_ops' was not declared. Should it be static? Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> 
Fix the following sparse warning:

drivers/pci/controller/pci-aardvark.c:469:28: warning:
 symbol 'advk_pci_bridge_emul_ops' was not declared. Should it be static?

Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>