linux-stable.git/drivers/net/phy/mscc, branch v5.7

net: phy: mscc: fix initialization of the MACsec protocol mode

2020-05-23T23:31:53+00:00

At the very end of the MACsec block initialization in the MSCC PHY
driver, the MACsec "protocol mode" is set. This setting should be set
based on the PHY id within the package, as the bank used to access the
register used depends on this. This was not done correctly, and only the
first bank was used leading to the two upper PHYs being unstable when
using the VSC8584. This patch fixes it.

Fixes: 1bbe0ecc2a1a ("net: phy: mscc: macsec initialization")
Signed-off-by: Antoine Tenart 
Signed-off-by: David S. Miller

net: phy: mscc: consolidate a common RGMII delay implementation

2020-03-24T23:36:37+00:00

It looks like the VSC8584 PHY driver is rolling its own RGMII delay
configuration code, despite the fact that the logic is mostly the same.

In fact only the register layout and position for the RGMII controls has
changed. So we need to adapt and parameterize the PHY-dependent bit
fields when calling the new generic function.

Signed-off-by: Vladimir Oltean 
Reviewed-by: Andrew Lunn 
Tested-by: Antoine Tenart 
Signed-off-by: David S. Miller

net: phy: mscc: add support for VSC8502

2020-03-24T03:52:27+00:00

This is a dual copper PHY with support for MII/GMII/RGMII on MAC side,
as well as a bunch of other features such as SyncE and Ring Resiliency.

I haven't tested interrupts and WoL, but I am confident that they work
since support is already present in the driver and the register map is
no different for this PHY.

PHY statistics work, PHY tunables appear to work, suspend/resume works.

Signed-off-by: Wes Li 
Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

net: phy: mscc: configure both RX and TX internal delays for RGMII

2020-03-24T03:52:27+00:00

The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.

Make them configurable instead, and add TX internal delays when
necessary too.

While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.

Signed-off-by: Vladimir Oltean 
Signed-off-by: David S. Miller

net: phy: mscc: accept all RGMII species in vsc85xx_mac_if_set

2020-03-24T03:52:26+00:00

The helper for configuring the pinout of the MII side of the PHY should
do so irrespective of whether RGMII delays are used or not. So accept
the ID, TXID and RXID variants as well, not just the no-delay RGMII
variant.

Signed-off-by: Vladimir Oltean 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay

2020-03-24T03:52:26+00:00

There is nothing RX-specific about these clock skew values. So remove
"RX" from the name in preparation for the next patch where TX delays are
also going to be configured.

Signed-off-by: Vladimir Oltean 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: mscc: RGMII skew delay configuration

2020-03-20T04:14:46+00:00

This patch adds support for configuring the RGMII skew delays in Rx and
Tx. The Rx and Tx skews are set based on the interface mode. By default
their configuration is set to the default value in hardware (0.2ns);
this means the driver do not rely anymore on the bootloader
configuration.

Then based on the interface mode being used, a 2ns delay is added:
- RGMII_ID adds it for both Rx and Tx.
- RGMII_RXID adds it for Rx.
- RGMII_TXID adds it for Tx.

Signed-off-by: Antoine Tenart 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: mscc: add support for RGMII MAC mode

2020-03-20T04:14:46+00:00

This patch adds support for connecting VSC8584 PHYs to the MAC using
RGMII.

Signed-off-by: Antoine Tenart 
Reviewed-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: mscc: add missing check on a phy_write return value

2020-03-20T04:02:38+00:00

Commit a5afc1678044 ("net: phy: mscc: add support for VSC8584 PHY")
introduced a call to 'phy_write' storing its return value to a variable
called 'ret'. But 'ret' never was checked for a possible error being
returned, and hence was not used at all. Fix this by checking the return
value and exiting the function if an error was returned.

As this does not fix a known bug, this commit is mostly cosmetic and not
sent as a fix.

Signed-off-by: Antoine Tenart 
Signed-off-by: David S. Miller

net: phy: mscc: consider interrupt source in interrupt handler

2020-03-18T03:58:22+00:00

Trigger the respective interrupt handler functionality only if the
related interrupt source bit is set.

Signed-off-by: Heiner Kallweit 
Signed-off-by: David S. Miller