linux-stable.git/drivers/net/phy/mscc, branch v5.13.2 Linux kernel stable tree net: phy: mscc: fix macsec key length 2021-07-14T15:07:19+00:00 Antoine Tenart atenart@kernel.org 2021-06-24T09:38:29+00:00 d22eadd94ca5a50e8f1acbc54bc72af456b00ec4 [ Upstream commit c309217f91f2d2097c2a0a832d9bff50b88c81dc ] The key length used to store the macsec key was set to MACSEC_KEYID_LEN (16), which is an issue as: - This was never meant to be the key length. - The key length can be > 16. Fix this by using MACSEC_MAX_KEY_LEN instead (the max length accepted in uAPI). Fixes: 28c5107aa904 ("net: phy: mscc: macsec support") Reported-by: Lior Nahmanson <liorna@nvidia.com> Signed-off-by: Antoine Tenart <atenart@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit c309217f91f2d2097c2a0a832d9bff50b88c81dc ]

The key length used to store the macsec key was set to MACSEC_KEYID_LEN
(16), which is an issue as:
- This was never meant to be the key length.
- The key length can be > 16.

Fix this by using MACSEC_MAX_KEY_LEN instead (the max length accepted in
uAPI).

Fixes: 28c5107aa904 ("net: phy: mscc: macsec support")
Reported-by: Lior Nahmanson <liorna@nvidia.com>
Signed-off-by: Antoine Tenart <atenart@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
net: phy: mscc: coma mode disabled for VSC8584 2021-03-19T19:17:30+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-03-19T13:29:05+00:00 36d021d1049f252c2bc1e20123b4cce9e9dc60af This patch releases coma mode for VSC8584 as done for VSC8514 in commit ca0d7fd0a58d ("net: phy: mscc: coma mode disabled for VSC8514") Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
This patch releases coma mode for VSC8584 as done for VSC8514 in
commit ca0d7fd0a58d ("net: phy: mscc: coma mode disabled for VSC8514")

Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.")
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: improved serdes calibration applied to VSC8584 2021-03-19T19:17:30+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-03-19T13:29:04+00:00 23d12335752fc08877d64719a679723d7e0a3962 Introduced 'FOJI' serdes calibration in commit 85e97f0b984e ("net: phy: mscc: improved serdes calibration applied to VSC8514") Now including the VSC8584 family. Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Introduced 'FOJI' serdes calibration in commit 85e97f0b984e
("net: phy: mscc: improved serdes calibration applied to VSC8514")
Now including the VSC8584 family.

Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.")
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: Applying LCPLL reset to VSC8584 2021-03-19T19:17:30+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-03-19T13:29:03+00:00 df4771783d6447b9c260bbb2692af15c4046c15b Introduced LCPLL reset in commit d15e08d9fb82 ("net: phy: mscc: adding LCPLL reset to VSC8514"). Now applying this reset to the VSC8584 phy familiy. Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.") Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Introduced LCPLL reset in
commit d15e08d9fb82 ("net: phy: mscc: adding LCPLL reset to VSC8514").
Now applying this reset to the VSC8584 phy familiy.

Fixes: a5afc1678044a ("net: phy: mscc: add support for VSC8584 PHY.")
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: coma mode disabled for VSC8514 2021-02-16T22:06:19+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-02-16T15:29:44+00:00 ca0d7fd0a58dfc9503775dae7daee341c115e0c7 The 'coma mode' (configurable through sw or hw) provides an optional feature that may be used to control when the PHYs become active. The typical usage is to synchronize the link-up time across all PHY instances. This patch releases coma mode if not done by hardware, otherwise the phys will not link-up. Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.") Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
The 'coma mode' (configurable through sw or hw) provides an
optional feature that may be used to control when the PHYs become active.
The typical usage is to synchronize the link-up time across
all PHY instances. This patch releases coma mode if not done by hardware,
otherwise the phys will not link-up.

Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: improved serdes calibration applied to VSC8514 2021-02-16T22:06:18+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-02-16T15:29:43+00:00 85e97f0b984eb36cba0ecaf87c66a9f7445d73dc The current IB serdes calibration algorithm (performed by the onboard 8051) has proven to be unstable for the VSC8514 QSGMII phy. A new algorithm has been developed based on 'Frequency-offset Jittered-Injection' or 'FoJi' method which solves all known issues. This patch disables the 8051 algorithm and replaces it with the new FoJi algorithm. The calibration is now performed in a new file (mscc_serdes.c), which can act as an placeholder for future serdes configurations. Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.") Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
The current IB serdes calibration algorithm (performed by the onboard 8051)
has proven to be unstable for the VSC8514 QSGMII phy.
A new algorithm has been developed based on
'Frequency-offset Jittered-Injection' or 'FoJi' method which solves
all known issues.  This patch disables the 8051 algorithm and
replaces it with the new FoJi algorithm.
The calibration is now performed in a new file (mscc_serdes.c),
which can act as an placeholder for future serdes configurations.

Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: adding LCPLL reset to VSC8514 2021-02-16T22:06:18+00:00 Bjarni Jonasson bjarni.jonasson@microchip.com 2021-02-16T15:29:42+00:00 3cc2c646be0b22037f31c958e96c0544a073d108 At Power-On Reset, transients may cause the LCPLL to lock onto a clock that is momentarily unstable. This is normally seen in QSGMII setups where the higher speed 6G SerDes is being used. This patch adds an initial LCPLL Reset to the PHY (first instance) to avoid this issue. Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.") Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
At Power-On Reset, transients may cause the LCPLL to lock onto a
clock that is momentarily unstable. This is normally seen in QSGMII
setups where the higher speed 6G SerDes is being used.
This patch adds an initial LCPLL Reset to the PHY (first instance)
to avoid this issue.

Fixes: e4f9ba642f0b ("net: phy: mscc: add support for VSC8514 PHY.")
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: mscc: use new PTP_MSGTYPE_* defines 2020-11-25T20:23:21+00:00 Christian Eggers ceggers@arri.de 2020-11-24T07:44:18+00:00 298722166ab2fdced64b2ccb2923720153ff2029 Use recently introduced PTP_MSGTYPE_SYNC and PTP_MSGTYPE_DELAY_REQ defines instead of a driver internal enumeration. Signed-off-by: Christian Eggers <ceggers@arri.de> Reviewed-by: Antoine Tenart <atenart@kernel.org> Acked-by: Richard Cochran <richardcochran@gmail.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Use recently introduced PTP_MSGTYPE_SYNC and PTP_MSGTYPE_DELAY_REQ
defines instead of a driver internal enumeration.

Signed-off-by: Christian Eggers <ceggers@arri.de>
Reviewed-by: Antoine Tenart <atenart@kernel.org>
Acked-by: Richard Cochran <richardcochran@gmail.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Merge https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 2020-11-20T03:08:46+00:00 Jakub Kicinski kuba@kernel.org 2020-11-20T03:08:46+00:00 56495a2442a47d0ea752db62434913b3346fe5a5 Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mscc: fix excluded_middle.cocci warnings 2020-11-17T17:27:39+00:00 kernel test robot lkp@intel.com 2020-11-16T15:34:44+00:00 b618c327024997589051ea3605b38d1f7ce138a7 Condition !A || A && B is equivalent to !A || B. Generated by: scripts/coccinelle/misc/excluded_middle.cocci Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Signed-off-by: Julia Lawall <julia.lawall@inria.fr> Reviewed-by: Antoine Tenart <atenart@kernel.org> Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2011161633240.2682@hadrien Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Condition !A || A && B is equivalent to !A || B.

Generated by: scripts/coccinelle/misc/excluded_middle.cocci

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@inria.fr>
Reviewed-by: Antoine Tenart <atenart@kernel.org>
Link: https://lore.kernel.org/r/alpine.DEB.2.22.394.2011161633240.2682@hadrien
Signed-off-by: Jakub Kicinski <kuba@kernel.org>