linux-stable.git/drivers/net/phy/mediatek, branch master

net: phy: mediatek: add phy driver for MT7628 built-in Fast Ethernet PHYs

2026-08-18T13:50:13+00:00

The Fast Ethernet PHYs present in the MT7628 SoCs require an
undocumented bit to be set before they can establish 100mbps links.

This commit adds the Kconfig option MEDIATEK_FE_SOC_PHY and the
corresponding driver mtk-fe-soc.c.

Signed-off-by: Joris Vaisvila 
Reviewed-by: Andrew Lunn 
Reviewed-by: Daniel Golle 
Link: https://patch.msgid.link/20260813190241.789323-3-joey@tinyisr.com
Signed-off-by: Paolo Abeni

net: phy: mediatek: add EcoNet EN7528 PHY support

2026-08-07T23:30:28+00:00

The EcoNet EN7528 MIPS SoC embeds four Gigabit Ethernet PHYs (PHY ID
0x03a29491) behind its built-in MT7530 switch. They use the same LED
register layout as the other SoC PHYs handled by this driver, but their
LED controller powers up with its external control disabled, so the LED
pins stay dark regardless of what is programmed into the LED control
registers.

Add a phy_driver entry for it, modelled on the Airoha AN7583 one. Its
config_init callback enables the LED controller through the LED basic
control register, which this driver does not program for its other
PHYs, but which the air_en8811h driver already handles as
AIR_PHY_LED_BCR. LED behaviour is then controlled through the phylib
LED operations shared with the other PHYs of this driver.

The LED block is shared by the four PHYs of the EN7528: the LED
configuration programmed through any one of them applies to all four,
while each PHY still drives its own LED pin from its own link state.

The EN7528 PHYs need no efuse calibration data, so relax the
MEDIATEK_GE_SOC_PHY dependencies to allow building the driver on the
ECONET platform.

Signed-off-by: Ahmed Naseef 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20260804103321.3331802-1-naseefkm@gmail.com
Signed-off-by: Jakub Kicinski

net: phy: mediatek: fix TX blink masks using the RX bits

2026-08-06T12:53:16+00:00

MTK_GPHY_LED_TX_BLINK_SET and MTK_2P5GPHY_LED_TX_BLINK_SET are built
from the RX blink bits instead of the TX ones, so both TX masks are
identical to their RX counterparts. The TX bits they should be using,
MTK_PHY_LED_BLINK_{10,100,1000,2500}TX, are otherwise only referenced
by the per-speed branch of mtk_phy_led_hw_ctrl_set().

A TX trigger selected without a link trigger therefore programs the RX
blink bits, and the LED blinks on received traffic. The masks are also
used to decode the blink register in mtk_phy_led_hw_ctrl_get(), which
as a result cannot tell the two triggers apart: an RX-only
configuration reads back as RX and TX, and a TX-only configuration
reads back as neither.

Fixes: 7f9c320c98db ("net: phy: mediatek: Move LED helper functions into mtk phy lib")
Cc: stable@vger.kernel.org
Signed-off-by: Ahmed Naseef 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20260804113511.3371248-1-naseefkm@gmail.com
Signed-off-by: Paolo Abeni

net: phy: mediatek: enable interrupts on AN7581

2026-01-06T00:16:53+00:00

Interrupts work just like on MT7988.

Suggested-by: Benjamin Larsson 
Signed-off-by: Aleksander Jan Bajkowski 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20260102113222.3519900-1-olek2@wp.pl
Signed-off-by: Jakub Kicinski

net: phy: mediatek: fix nvmem cell reference leak in mt798x_phy_calibration

2025-12-22T11:18:54+00:00

When nvmem_cell_read() fails in mt798x_phy_calibration(), the function
returns without calling nvmem_cell_put(), leaking the cell reference.

Move nvmem_cell_put() right after nvmem_cell_read() to ensure the cell
reference is always released regardless of the read result.

Found via static analysis and code review.

Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
Cc: stable@vger.kernel.org
Signed-off-by: Miaoqian Lin 
Reviewed-by: Daniel Golle 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20251211081313.2368460-1-linmq006@gmail.com
Signed-off-by: Paolo Abeni

net: phy: mtk-2p5ge: Add LED support for MT7988

2025-08-28T23:43:21+00:00

Add LED support for MT7988's built-in 2.5Gphy. LED hardware has almost
the same design with MT7981's/MT7988's built-in GbE. So hook the same
helper function here.

Before mtk_phy_leds_state_init(), set correct default values of LED0
and LED1.

Signed-off-by: Sky Huang 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250827044755.3256991-1-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski

net: phy: add Kconfig symbol PHY_PACKAGE

2025-06-16T21:59:30+00:00

Only a handful of PHY drivers needs the PHY package functionality,
therefore build the module only if needed.

Signed-off-by: Heiner Kallweit 
Link: https://patch.msgid.link/42c05496-61b2-4b09-b853-3d99b3dfe95c@gmail.com
Signed-off-by: Jakub Kicinski

net: phy: mediatek: Add Airoha AN7583 PHY support

2025-05-28T00:07:53+00:00

Add Airoha AN7583 PHY support based on Airoha AN7581 with the small
difference that BMCR_PDOWN is enabled by default and needs to be cleared
to make the internal PHY correctly work.

Signed-off-by: Christian Marangi 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250522165313.6411-4-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski

net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988

2025-05-21T01:11:04+00:00

Add support for internal 2.5Gphy on MT7988. This driver will load
necessary firmware and add appropriate time delay to make sure
that firmware works stably. The firmware loading procedure takes
about 11ms in this driver.

Signed-off-by: Sky Huang 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250516102327.2014531-3-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski

net: phy: mediatek: Sort config and file names in Kconfig and Makefile

2025-05-21T01:11:04+00:00

Sort config and file names in Kconfig and Makefile in
drivers/net/phy/mediatek/ in alphabetical order.

Signed-off-by: Sky Huang 
Reviewed-by: Andrew Lunn 
Link: https://patch.msgid.link/20250516102327.2014531-2-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski