linux-stable.git/drivers/net/phy/mediatek, branch linux-6.16.y Linux kernel stable tree net: phy: mediatek: Add Airoha AN7583 PHY support 2025-05-28T00:07:53+00:00 Christian Marangi ansuelsmth@gmail.com 2025-05-22T16:53:11+00:00 8bc3c234dcb65a018120dab96c83845cc7ff35c6 Add Airoha AN7583 PHY support based on Airoha AN7581 with the small difference that BMCR_PDOWN is enabled by default and needs to be cleared to make the internal PHY correctly work. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250522165313.6411-4-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Add Airoha AN7583 PHY support based on Airoha AN7581 with the small
difference that BMCR_PDOWN is enabled by default and needs to be cleared
to make the internal PHY correctly work.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250522165313.6411-4-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: add driver for built-in 2.5G ethernet PHY on MT7988 2025-05-21T01:11:04+00:00 Sky Huang skylake.huang@mediatek.com 2025-05-16T10:23:27+00:00 26948c2430412b667fcc2302dcff15ca45b3cd52 Add support for internal 2.5Gphy on MT7988. This driver will load necessary firmware and add appropriate time delay to make sure that firmware works stably. The firmware loading procedure takes about 11ms in this driver. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250516102327.2014531-3-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Add support for internal 2.5Gphy on MT7988. This driver will load
necessary firmware and add appropriate time delay to make sure
that firmware works stably. The firmware loading procedure takes
about 11ms in this driver.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250516102327.2014531-3-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: Sort config and file names in Kconfig and Makefile 2025-05-21T01:11:04+00:00 Sky Huang skylake.huang@mediatek.com 2025-05-16T10:23:26+00:00 6d243c80fe9178878f4924804d35f1ed24f590cb Sort config and file names in Kconfig and Makefile in drivers/net/phy/mediatek/ in alphabetical order. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250516102327.2014531-2-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Sort config and file names in Kconfig and Makefile in
drivers/net/phy/mediatek/ in alphabetical order.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250516102327.2014531-2-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: do not require syscon compatible for pio property 2025-05-16T22:40:51+00:00 Frank Wunderlich frank-w@public-files.de 2025-05-10T17:49:32+00:00 15d7b3dfafa98270eade6c77d2336790dde0a40d Current implementation requires syscon compatible for pio property which is used for driving the switch leds on mt7988. Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and device_node_to_regmap to get the regmap already assigned by pinctrl driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Link: https://patch.msgid.link/20250510174933.154589-1-linux@fw-web.de Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Current implementation requires syscon compatible for pio property
which is used for driving the switch leds on mt7988.

Replace syscon_regmap_lookup_by_phandle with of_parse_phandle and
device_node_to_regmap to get the regmap already assigned by pinctrl
driver.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Link: https://patch.msgid.link/20250510174933.154589-1-linux@fw-web.de
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: init val in .phy_led_polarity_set for AN7581 2025-04-17T01:26:42+00:00 Christian Marangi ansuelsmth@gmail.com 2025-04-15T10:53:05+00:00 00868d0348187fe1123324f77e069a916f932037 Fix smatch warning for uninitialised val in .phy_led_polarity_set for AN7581 driver. Correctly init to 0 to set polarity high by default. Reported-by: Simon Horman <horms@kernel.org> Fixes: 6a325aed130b ("net: phy: mediatek: add Airoha PHY ID to SoC driver") Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://patch.msgid.link/20250415105313.3409-1-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Fix smatch warning for uninitialised val in .phy_led_polarity_set for
AN7581 driver.

Correctly init to 0 to set polarity high by default.

Reported-by: Simon Horman <horms@kernel.org>
Fixes: 6a325aed130b ("net: phy: mediatek: add Airoha PHY ID to SoC driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20250415105313.3409-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: add Airoha PHY ID to SoC driver 2025-04-12T03:18:31+00:00 Christian Marangi ansuelsmth@gmail.com 2025-04-10T10:04:04+00:00 6a325aed130bb68790e765f923e76ec5669d2da7 Airoha AN7581 SoC ship with a Switch based on the MT753x Switch embedded in other SoC like the MT7581 and the MT7988. Similar to these they require configuring some pin to enable LED PHYs. Add support for the PHY ID for the Airoha embedded Switch and define a simple probe function to toggle these pins. Also fill the LED functions and add dedicated function to define LED polarity. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Link: https://patch.msgid.link/20250410100410.348-2-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Airoha AN7581 SoC ship with a Switch based on the MT753x Switch embedded
in other SoC like the MT7581 and the MT7988. Similar to these they
require configuring some pin to enable LED PHYs.

Add support for the PHY ID for the Airoha embedded Switch and define a
simple probe function to toggle these pins. Also fill the LED functions
and add dedicated function to define LED polarity.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20250410100410.348-2-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: permit to compile test GE SOC PHY driver 2025-04-12T03:18:31+00:00 Christian Marangi ansuelsmth@gmail.com 2025-04-10T10:04:03+00:00 e5566162af8b9690e096d2e6089e4ed955a0d13d When commit 462a3daad679 ("net: phy: mediatek: fix compile-test dependencies") fixed the dependency, it should have also introduced an or on COMPILE_TEST to permit this driver to be compile-tested even if NVMEM_MTK_EFUSE wasn't selected. The driver makes use of NVMEM API that are always compiled (return error) so the driver can actually be compiled even without that config. Fix and simplify the dependency condition of this kernel config. Fixes: 462a3daad679 ("net: phy: mediatek: fix compile-test dependencies") Acked-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20250410100410.348-1-ansuelsmth@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
When commit 462a3daad679 ("net: phy: mediatek: fix compile-test
dependencies") fixed the dependency, it should have also introduced
an or on COMPILE_TEST to permit this driver to be compile-tested even if
NVMEM_MTK_EFUSE wasn't selected. The driver makes use of NVMEM API that
are always compiled (return error) so the driver can actually be
compiled even without that config.

Fix and simplify the dependency condition of this kernel config.

Fixes: 462a3daad679 ("net: phy: mediatek: fix compile-test dependencies")
Acked-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Link: https://patch.msgid.link/20250410100410.348-1-ansuelsmth@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: use new phy_package_shared getters 2025-03-06T03:13:53+00:00 Heiner Kallweit hkallweit1@gmail.com 2025-03-03T20:17:18+00:00 dc5a6164fedacdcdbb51a2a340ca264191a5b82c Use the new getters for members of struct phy_package_shared. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://patch.msgid.link/356a257f-68d0-47bc-a474-4dafaeaa149f@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Use the new getters for members of struct phy_package_shared.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://patch.msgid.link/356a257f-68d0-47bc-a474-4dafaeaa149f@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: Move some macros to phy-lib for later use 2025-02-18T00:22:36+00:00 Sky Huang skylake.huang@mediatek.com 2025-02-13T08:05:53+00:00 be378ebd6cfb8e369d4aa03a551e594d00debda5 Move some macros to phy-lib because MediaTek's 2.5G built-in ethernet PHY will also use them. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Move some macros to phy-lib because MediaTek's 2.5G built-in
ethernet PHY will also use them.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-6-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
net: phy: mediatek: Add token ring clear bit operation support 2025-02-18T00:22:36+00:00 Sky Huang skylake.huang@mediatek.com 2025-02-13T08:05:52+00:00 4786eff288bcc77a5dbc2be2308f46f70e58600d Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c, we clear some register bits via token ring, which were also implemented in three __phy_write(). Now we can do the same thing via __mtk_tr_clr_bits() helper. Signed-off-by: Sky Huang <skylake.huang@mediatek.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> 
Similar to __mtk_tr_set_bits() support. Previously in mtk-ge-soc.c,
we clear some register bits via token ring, which were also implemented
in three __phy_write(). Now we can do the same thing via
__mtk_tr_clr_bits() helper.

Signed-off-by: Sky Huang <skylake.huang@mediatek.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20250213080553.921434-5-SkyLake.Huang@mediatek.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>