linux-stable.git/drivers/net/phy/broadcom.c, branch linux-4.19.y

net: phy: broadcom: stub c45 read/write for 54810

2023-08-30T14:31:50+00:00

commit 096516d092d54604d590827d05b1022c8f326639 upstream.

The 54810 does not support c45. The mmd_phy_indirect accesses return
arbirtary values leading to odd behavior like saying it supports EEE
when it doesn't. We also see that reading/writing these non-existent
MMD registers leads to phy instability in some cases.

Fixes: b14995ac2527 ("net: phy: broadcom: Add BCM54810 PHY entry")
Signed-off-by: Justin Chen 
Reviewed-by: Florian Fainelli 
Link: https://lore.kernel.org/r/1691901708-28650-1-git-send-email-justin.chen@broadcom.com
Signed-off-by: Jakub Kicinski 
[florian: resolved conflicts in 4.19]
Signed-off-by: Florian Fainelli 
Signed-off-by: Greg Kroah-Hartman

net: phy: broadcom: Fix brcm_fet_config_init()

2022-04-15T12:14:53+00:00

[ Upstream commit bf8bfc4336f7a34e48b3bbd19b1542bf085bdc3d ]

A Broadcom AC201 PHY (same entry as 5241) would be flagged by the
Broadcom UniMAC MDIO controller as not completing the turn around
properly since the PHY expects 65 MDC clock cycles to complete a write
cycle, and the MDIO controller was only sending 64 MDC clock cycles as
determined by looking at a scope shot.

This would make the subsequent read fail with the UniMAC MDIO controller
command field having MDIO_READ_FAIL set and we would abort the
brcm_fet_config_init() function and thus not probe the PHY at all.

After issuing a software reset, wait for at least 1ms which is well
above the 1us reset delay advertised by the datasheet and issue a dummy
read to let the PHY turn around the line properly. This read
specifically ignores -EIO which would be returned by MDIO controllers
checking for the line being turned around.

If we have a genuine reaad failure, the next read of the interrupt
status register would pick it up anyway.

Fixes: d7a2ed9248a3 ("broadcom: Add AC131 phy support")
Signed-off-by: Florian Fainelli 
Link: https://lore.kernel.org/r/20220324232438.1156812-1-f.fainelli@gmail.com
Signed-off-by: Jakub Kicinski 
Signed-off-by: Sasha Levin

net: phy: broadcom: Enable 125 MHz clock on LED4 pin for BCM54612E by default.

2018-06-05T13:43:09+00:00

BCM54612E have 4 multi-functional LED pins that can be configured
through register setting; the LED4 pin can be configured to a 125MHz
reference clock output by setting the spare register. Since the dedicated
CLK125 reference clock pin is not brought out on the 48-Pin MLP, the LED4
pin is the only pin to provide such function in this package, and therefore
it is beneficial to just enable the reference clock by default.

Signed-off-by: Kun Yi 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: broadcom: add support for BCM89610 PHY

2018-05-04T16:45:55+00:00

It adds support for BCM89610 (Single-Port 10/100/1000BASE-T)
transceiver which is used in P3310 Tegra186 platform.

Signed-off-by: Bhadram Varka 
Signed-off-by: David S. Miller

net: phy: broadcom: Add entry for 5395 switch PHYs

2017-12-15T20:41:13+00:00

Add an entry for the builtin PHYs present in the Broadcom BCM5395 switch. This
allows us to retrieve the PHY statistics among other things.

Signed-off-by: Florian Fainelli 
Tested-by: Chris Healy 
Signed-off-by: David S. Miller

net: phy: broadcom: re-add mistakenly removed config settings

2017-12-04T16:17:08+00:00

Previous patch mistakenly removed three chip-specific config settings.
Add them again.

Fixes: 80274abafc60 "net: phy: remove generic settings for callbacks config_aneg and read_status from drivers"
Signed-off-by: Heiner Kallweit 
Signed-off-by: David S. Miller

net: phy: remove generic settings for callbacks config_aneg and read_status from drivers

2017-12-01T20:42:21+00:00

Remove generic settings for callbacks config_aneg and read_status
from drivers.

Signed-off-by: Heiner Kallweit 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: phy: broadcom: support new device flag for setting master mode

2017-10-13T05:59:38+00:00

Some of Broadcom's PHYs run by default in slave mode with Automatic
Slave/Master configuration disabled. It stops them from working properly
with some devices.

So far it has been verified for BCM54210E and BCM50212E which don't
work well with Intel's I217-LM and I218-LM:
http://ark.intel.com/products/60019/Intel-Ethernet-Connection-I217-LM
http://ark.intel.com/products/71307/Intel-Ethernet-Connection-I218-LM
I was told there is massive ping loss.

This commit adds support for a new flag which can be set by an ethernet
driver to fixup PHY setup.

Signed-off-by: Rafał Miłecki 
Signed-off-by: David S. Miller

net: phy: Remove residual magic from PHY drivers

2017-05-16T19:58:18+00:00

commit fa8cddaf903c ("net phylib: Remove unnecessary condition check in phy")
removed the only place where the PHY flag PHY_HAS_MAGICANEG was
checked. But it left the flag being set in the drivers. Remove the flag.

Signed-off-by: Andrew Lunn 
Signed-off-by: David S. Miller

net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay

2017-05-01T02:56:19+00:00

This patch allows users to enable/disable internal TX and/or RX
clock delay for BCM5481x series PHYs so as to satisfy RGMII timing
specifications.

On a particular platform, whether TX and/or RX clock delay is required
depends on how PHY connected to the MAC IP. This requirement can be
specified through "phy-mode" property in the platform device tree.

Signed-off-by: Abhishek Shah 
Reviewed-by: Florian Fainelli 
Signed-off-by: David S. Miller