linux-stable.git/drivers/net/phy/Makefile, branch linux-4.9.y Linux kernel stable tree net: phy: Sort Makefile and Kconfig 2016-08-20T00:11:50+00:00 Andrew Lunn andrew@lunn.ch 2016-08-18T21:56:05+00:00 d75b4a22b255471906e794fe988b18de158cedec Sort the files to reduce merge conflicts and to make it easier to find drivers by name. Also separate the MDIO bus drivers from the PHY drivers, again to help find what you need. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Sort the files to reduce merge conflicts and to make it easier to find
drivers by name. Also separate the MDIO bus drivers from the PHY
drivers, again to help find what you need.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: Add gmiitorgmii converter support 2016-08-12T23:57:20+00:00 Appana Durga Kedareswara Rao appana.durga.rao@xilinx.com 2016-08-10T05:50:08+00:00 f411a6160bd4278508b5892949ba1a7db6f73489 This patch adds support for gmiitorgmii converter. The GMII to RGMII IP core provides the Reduced Gigabit Media Independent Interface (RGMII) between Ethernet physical media Devices and the Gigabit Ethernet controller. This core can Switch dynamically between the three different speed modes of Operation by configuring the converter register through mdio write. MDIO interface is used to set operating speed of Ethernet MAC. This converter sits between the MAC and the external phy MAC <==> GMII2RGMII <==> RGMII_PHY Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
This patch adds support for gmiitorgmii converter.

The GMII to RGMII IP core provides the Reduced Gigabit Media
Independent Interface (RGMII) between Ethernet physical media
Devices and the Gigabit Ethernet controller. This core can
Switch dynamically between the three different speed modes of
Operation by configuring the converter register through mdio write.

MDIO interface is used to set operating speed of Ethernet MAC.

This converter sits between the MAC and the external phy
MAC <==> GMII2RGMII <==> RGMII_PHY

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Microsemi VSC 8531/41 PHY Driver 2016-08-08T23:15:57+00:00 Raju Lakkaraju Raju.Lakkaraju@microsemi.com 2016-08-05T12:24:21+00:00 d50736a853b8633ed8c9c64a2a1487e6081b739c Hello, I added all review comments and re-sending for review. >From a5017f5878a92d2acec86a6a29b1498c457cb73a Mon Sep 17 00:00:00 2001 From: Nagaraju Lakkaraju <Raju.Lakkaraju@microsemi.com> Date: Wed, 3 Aug 2016 18:28:24 +0530 Subject: [PATCH v2] net: phy: Add drivers for Microsemi PHYs Signed-off-by: Nagaraju Lakkaraju <Raju.Lakkaraju@microsemi.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Hello,

I added all review comments and re-sending for review.

>From a5017f5878a92d2acec86a6a29b1498c457cb73a Mon Sep 17 00:00:00 2001
From: Nagaraju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Date: Wed, 3 Aug 2016 18:28:24 +0530
Subject: [PATCH v2] net: phy: Add drivers for Microsemi PHYs

Signed-off-by: Nagaraju Lakkaraju <Raju.Lakkaraju@microsemi.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers: net: phy: xgene: Add MDIO driver 2016-07-26T04:51:43+00:00 Iyappan Subramanian isubramanian@apm.com 2016-07-26T00:12:40+00:00 43b3cf6634a4ae2eac3b6f08019db8f19a114811 Currently, SGMII based 1G rely on the hardware registers for link state and sometimes it's not reliable. To get most accurate link state, this interface has to use the MDIO bus to poll the PHY. In X-Gene SoC, MDIO bus is shared across RGMII and SGMII based 1G interfaces, so adding this driver to manage MDIO bus. This driver registers the mdio bus and registers the PHYs connected to it. Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Tested-by: Fushen Chen <fchen@apm.com> Tested-by: Toan Le <toanle@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
Currently, SGMII based 1G rely on the hardware registers for link state
and sometimes it's not reliable.  To get most accurate link state, this
interface has to use the MDIO bus to poll the PHY.

In X-Gene SoC, MDIO bus is shared across RGMII and SGMII based 1G
interfaces, so adding this driver to manage MDIO bus.  This driver
registers the mdio bus and registers the PHYs connected to it.

Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Tested-by: Fushen Chen <fchen@apm.com>
Tested-by: Toan Le <toanle@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: Add MDIO bus driver for the Hisilicon FEMAC 2016-07-17T04:32:58+00:00 Dongpo Li lidongpo@hisilicon.com 2016-07-15T08:26:33+00:00 4960e4b1e69908ee70c716755a9415079e0d554f This patch adds a separate driver for the MDIO interface of the Hisilicon Fast Ethernet MAC. Signed-off-by: Dongpo Li <lidongpo@hisilicon.com> Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net> 
This patch adds a separate driver for the MDIO interface of the
Hisilicon Fast Ethernet MAC.

Signed-off-by: Dongpo Li <lidongpo@hisilicon.com>
Reviewed-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
phy: move fixed_phy MII register generation to a library 2016-06-27T14:40:57+00:00 Russell King rmk+kernel@arm.linux.org.uk 2016-06-23T13:50:05+00:00 5ae68b0ce134f9cadae2668da82d5f9a77523314 Move the fixed_phy MII register generation to a library to allow other software phy implementations to use this code. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net> 
Move the fixed_phy MII register generation to a library to allow other
software phy implementations to use this code.

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: mdio-mux: Add MDIO mux driver for iProc SoCs 2016-06-11T06:24:54+00:00 Pramod Kumar pramod.kumar@broadcom.com 2016-06-10T05:33:49+00:00 98bc865a1ec8074defd168b0feb9c466eeaeff33 iProc based SoCs supports the integrated mdio multiplexer which has the bus selection as well as mdio transaction generation logic inside. This multiplexer has child buses for PCIe, SATA, USB and ETH. These buses could be internal or external to SOC where PHYs are attached. These buses could use C-45 or C-22 mdio transaction. Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
iProc based SoCs supports the integrated mdio multiplexer which
has the bus selection as well as mdio transaction generation logic
inside.

This multiplexer has child buses for PCIe, SATA, USB and ETH. These
buses could be internal or external to SOC where PHYs are attached.
These buses could use C-45 or C-22 mdio transaction.

Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
NET: PHY: adds driver for Intel XWAY PHY 2016-06-11T05:13:48+00:00 Hauke Mehrtens hauke@hauke-m.de 2016-06-05T21:41:11+00:00 112b558d025712c0bbcefa3d07a4433dd3e32d27 This adds support for the Intel (former Lantiq) XWAY 11G and 22E PHYs. These PHYs are also named PEF 7061, PEF 7071, PEF 7072. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net> 
This adds support for the Intel (former Lantiq) XWAY 11G and 22E PHYs.
These PHYs are also named PEF 7061, PEF 7071, PEF 7072.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
phy: mdio-thunder: Add driver for Cavium Thunder SoC MDIO buses. 2016-03-14T19:27:22+00:00 David Daney david.daney@cavium.com 2016-03-11T17:53:11+00:00 379d7ac7ca31722a1fb488ae3e98b274c9db568c The Cavium Thunder SoCs have multiple MIDO buses that are part of a single PCI device. To model this in the device tree we call the PCI parent device a "cavium,thunder-8890-mdio-nexus", it has several children, one for each MDIO bus. The MDIO bus hardware is identical to that found in the OCTEON SoCs, so we use that code for things that are not part of the PCI driver probe/remove Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
The Cavium Thunder SoCs have multiple MIDO buses that are part of a
single PCI device.  To model this in the device tree we call the PCI
parent device a "cavium,thunder-8890-mdio-nexus", it has several
children, one for each MDIO bus.

The MDIO bus hardware is identical to that found in the OCTEON SoCs,
so we use that code for things that are not part of the PCI driver
probe/remove

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
phy: mdio-octeon: Refactor into two files/modules 2016-03-14T19:27:22+00:00 David Daney david.daney@cavium.com 2016-03-11T17:53:10+00:00 1eefee901fca0208b8a56f20cdc134e2b8638ae7 A follow-on patch uses PCI probing to find the Thunder MDIO hardware. In preparation for this, split out the common code into a new file mdio-cavium.c, which will be used by both the existing OCTEON driver, and the new Thunder PCI based driver. As part of the refactoring simplify the struct cavium_mdiobus by removing fields that are only ever used in the probe function and can just as well be local variables. Use readq/writeq in preference to readq_relaxed/writeq_relaxed as the relaxed form was an optimization for an early chip revision, and the MDIO drivers are not performance bottlenecks that need optimization in the first place. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
A follow-on patch uses PCI probing to find the Thunder MDIO hardware.
In preparation for this, split out the common code into a new file
mdio-cavium.c, which will be used by both the existing OCTEON driver,
and the new Thunder PCI based driver.

As part of the refactoring simplify the struct cavium_mdiobus by
removing fields that are only ever used in the probe function and can
just as well be local variables.

Use readq/writeq in preference to readq_relaxed/writeq_relaxed as the
relaxed form was an optimization for an early chip revision, and the
MDIO drivers are not performance bottlenecks that need optimization in
the first place.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>