linux-stable.git/drivers/mtd/devices, branch v4.13

Merge tag 'spi-nor/for-4.13' into MTD

2017-07-08T01:00:06+00:00

From Cyrille:
"""
This pull request contains the following notable changes:
- introduce support to the SPI 1-2-2 and 1-4-4 protocols.
- introduce support to the Double Data Rate (DDR) mode.
- introduce support to the Octo SPI protocols.
- add support to new memory parts for Spansion, Macronix and Winbond.
- add fixes for the Aspeed, STM32 and Cadence QSPI controler drivers.
- clean up the st_spi_fsm driver.
"""

mtd: st_spi_fsm: remove SPINOR_OP_RDSR2 and use SPINOR_OP_RDCR instead

2017-06-27T19:50:17+00:00

The 35h instruction op code has two aliases/macro definitions:
- SPINOR_OP_RDCR from include/linux/mtd/spi-nor.h
- SPINOR_OP_RDSR2 from drivers/mtd/devices/serial_flash_cmds.h

Actually, some manufacturers name the associated internal register Status
Register 2 whereas other manufacturers name it Configuration Register
hence the two different macros for the very same instruction op code.

Since the spi-nor.h file is the reference file for all SPI NOR instruction
op codes, this patch removes the definition of the SPINOR_OP_RDSR2 macro.

Also the SPINOR_OP_RDSR2 macro will be associated to another instruction
op code in a further patch so we need to avoid a conflict defining this
macro twice. Indeed the JESD216 rev B specification, defining the SFDP
tables, also refers to the 3Eh and 3Fh instruction op codes to write/read
the Status Register 2 on some SPI NOR flash memories, the 35h op code
still being used to read the Configuration Register/Status Register 2 on
other memories.

Signed-off-by: Cyrille Pitchen 
Acked-by: Marek Vasut

mtd: mchp23k256: Add support for mchp23lcv1024

2017-06-08T23:32:11+00:00

The mchp23lcv1024 is similar to the mchp23k256, the differences (from a
software point of view) are the capacity of the chip and the size of the
addresses used.

There is no way to detect the specific chip so we must be told via a
Device Tree or default to mchp23k256 when device tree is not used.

Signed-off-by: Chris Packham 
Reviewed-by: Andrew Lunn 
Acked-by: Rob Herring 
Signed-off-by: Brian Norris

mtd: mchp23k256: add partitioning support

2017-06-08T23:28:03+00:00

Setting the of_node for the mtd device allows the generic mtd code to
setup the partitions.

[Editorial note (Brian): patch still pending on fixing up the "aligned
to eraseblock" partition sanity check, given that this SRAM has no
eraseblocks.]

Signed-off-by: Chris Packham 
Reviewed-by: Andrew Lunn 
Tested-by: Andrew Lunn 
Signed-off-by: Brian Norris

mtd: mchp23k256: switch to mtd_device_register()

2017-06-01T18:28:54+00:00

Use mtd_device_register() instead of mtd_device_parse_register() to
eliminate two unused parameters.

Signed-off-by: Chris Packham 
Reviewed-by: Andrew Lunn 
Tested-by: Andrew Lunn 
Acked-by: Boris Brezillon 
Signed-off-by: Brian Norris

mtd: mchp23k256: Add OF device ID table

2017-06-01T18:28:53+00:00

This allows registering of this device via a Device Tree.

Signed-off-by: Chris Packham 
Reviewed-by: Andrew Lunn 
Tested-by: Andrew Lunn 
Acked-by: Boris Brezillon 
Acked-by: Rob Herring 
Signed-off-by: Brian Norris

mtd: m25p80: add support of SPI 1-2-2 and 1-4-4 protocols

2017-05-15T19:56:17+00:00

Before this patch, m25p80_read() supported few SPI protocols:
- regular SPI 1-1-1
- SPI Dual Output 1-1-2
- SPI Quad Output 1-1-4
On the other hand, m25p80_write() only supported SPI 1-1-1.

This patch updates both m25p80_read() and m25p80_write() functions to let
them support SPI 1-2-2 and SPI 1-4-4 protocols for Fast Read and Page
Program SPI commands.

It adopts a conservative approach to avoid regressions. Hence the new
implementations try to be as close as possible to the old implementations,
so the main differences are:
- the tx_nbits values now being set properly for the spi_transfer
  structures carrying the (op code + address/dummy) bytes
- and the spi_transfer structure being split into 2 spi_transfer
  structures when the numbers of I/O lines are different for op code and
  for address/dummy byte transfers on the SPI bus.

Besides, the current spi-nor framework supports neither the SPI 2-2-2 nor
the SPI 4-4-4 protocols. So, for now, we don't need to update the
m25p80_{read|write}_reg() functions as SPI 1-1-1 is the only one possible
protocol.

Signed-off-by: Cyrille Pitchen 
Reviewed-by: Marek Vasut

mtd: spi-nor: introduce SPI 1-2-2 and SPI 1-4-4 protocols

2017-05-15T19:56:17+00:00

This patch changes the prototype of spi_nor_scan(): its 3rd parameter
is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
framework about the actual hardware capabilities supported by the SPI
controller and its driver.

Besides, this patch also introduces a new 'struct spi_nor_flash_parameter'
telling the spi-nor framework about the hardware capabilities supported by
the SPI flash memory and the associated settings required to use those
hardware caps.

Then, to improve the readability of spi_nor_scan(), the discovery of the
memory settings and the memory initialization are now split into two
dedicated functions.

1 - spi_nor_init_params()

The spi_nor_init_params() function is responsible for initializing the
'struct spi_nor_flash_parameter'. Currently this structure is filled with
legacy values but further patches will allow to override some parameter
values dynamically, for instance by reading the JESD216 Serial Flash
Discoverable Parameter (SFDP) tables from the SPI memory.
The spi_nor_init_params() function only deals with the hardware
capabilities of the SPI flash memory: especially it doesn't care about
the hardware capabilities supported by the SPI controller.

2 - spi_nor_setup()

The second function is called once the 'struct spi_nor_flash_parameter'
has been initialized by spi_nor_init_params().
With both 'struct spi_nor_flash_parameter' and 'struct spi_nor_hwcaps',
the new argument of spi_nor_scan(), spi_nor_setup() computes the best
match between hardware caps supported by both the (Q)SPI memory and
controller hence selecting the relevant settings for (Fast) Read and Page
Program operations.

Signed-off-by: Cyrille Pitchen 
Reviewed-by: Marek Vasut

mtd: mchp23k256: Add driver for this SPI SRAM device

2017-05-11T17:13:02+00:00

The Microchip 23k256 is a 32K Byte SRAM connected via SPI.

Signed-off-by: Andrew Lunn 
Reviewed-by: Boris Brezillon 
Reviewed-by: Cyrille Pitchen 
[Brian: fixed copyright to be in this millenium]
Signed-off-by: Brian Norris

mtd: dataflash: Add flash_info for AT45DB641E

2017-05-11T17:04:52+00:00

Cc: cphealy@gmail.com
Cc: David Woodhouse 
Cc: Brian Norris 
Cc: Boris Brezillon 
Cc: Marek Vasut 
Cc: Richard Weinberger 
Cc: Cyrille Pitchen 
Cc: linux-kernel@vger.kernel.org
Acked-by: Marek Vasut 
Tested-by: Chris Healy 
Signed-off-by: Andrey Smirnov 
Signed-off-by: Brian Norris