linux-stable.git/drivers/mmc, branch linux-3.16.y

mmc: spi: Toggle SPI polarity, do not hardcode it

2020-05-22T20:19:16+00:00

commit af3ed119329cf9690598c5a562d95dfd128e91d6 upstream.

The code in mmc_spi_initsequence() tries to send a burst with
high chipselect and for this reason hardcodes the device into
SPI_CS_HIGH.

This is not good because the SPI_CS_HIGH flag indicates
logical "asserted" CS not always the physical level. In
some cases the signal is inverted in the GPIO library and
in that case SPI_CS_HIGH is already set, and enforcing
SPI_CS_HIGH again will actually drive it low.

Instead of hard-coding this, toggle the polarity so if the
default is LOW it goes high to assert chipselect but if it
is already high then toggle it low instead.

Cc: Phil Elwell 
Reported-by: Mark Brown 
Signed-off-by: Linus Walleij 
Reviewed-by: Mark Brown 
Link: https://lore.kernel.org/r/20191204152749.12652-1-linus.walleij@linaro.org
Signed-off-by: Ulf Hansson 
Signed-off-by: Ben Hutchings

mmc: sdhci: fix minimum clock rate for v3 controller

2020-04-28T18:03:33+00:00

commit 2a187d03352086e300daa2044051db00044cd171 upstream.

For SDHCIv3+ with programmable clock mode, minimal clock frequency is
still base clock / max(divider). Minimal programmable clock frequency is
always greater than minimal divided clock frequency. Without this patch,
SDHCI uses out-of-spec initial frequency when multiplier is big enough:

mmc1: mmc_rescan_try_freq: trying to init card at 468750 Hz
[for 480 MHz source clock divided by 1024]

The code in sdhci_calc_clk() already chooses a correct SDCLK clock mode.

Fixes: c3ed3877625f ("mmc: sdhci: add support for programmable clock mode")
Signed-off-by: Michał Mirosław 
Acked-by: Adrian Hunter 
Link: https://lore.kernel.org/r/ffb489519a446caffe7a0a05c4b9372bd52397bb.1579082031.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Ulf Hansson 
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings

mmc: sdhci-s3c: solve problem with sleeping in atomic context

2020-02-11T20:03:57+00:00

commit 017210d1c0dc2e2d3b142985cb31d90b98dc0f0f upstream.

This change addresses following problem:

[    2.560726] ------------[ cut here ]------------
[    2.565341] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2744 lockdep_trace_alloc+0xec/0x118()
[    2.574439] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
[    2.579821] Modules linked in:
[    2.583038] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W      3.18.0-next-20141216-00002-g4ff197fc1902-dirty #1318
[    2.593796] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[    2.599892] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    2.607612] [] (show_stack) from [] (dump_stack+0x70/0xbc)
[    2.614822] [] (dump_stack) from [] (warn_slowpath_common+0x74/0xb0)
[    2.622885] [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[    2.631569] [] (warn_slowpath_fmt) from [] (lockdep_trace_alloc+0xec/0x118)
[    2.640246] [] (lockdep_trace_alloc) from [] (__kmalloc+0x3c/0x1cc)
[    2.648240] [] (__kmalloc) from [] (clk_fetch_parent_index+0xb8/0xd4)
[    2.656390] [] (clk_fetch_parent_index) from [] (clk_calc_new_rates+0xe0/0x1fc)
[    2.665415] [] (clk_calc_new_rates) from [] (clk_calc_new_rates+0x1b4/0x1fc)
[    2.674181] [] (clk_calc_new_rates) from [] (clk_set_rate+0x50/0xc8)
[    2.682265] [] (clk_set_rate) from [] (sdhci_cmu_set_clock+0x68/0x16c)
[    2.690503] [] (sdhci_cmu_set_clock) from [] (sdhci_do_set_ios+0xf0/0x64c)
[    2.699095] [] (sdhci_do_set_ios) from [] (sdhci_set_ios+0x20/0x2c)
[    2.707080] [] (sdhci_set_ios) from [] (mmc_power_up+0x118/0x1fc)
[    2.714889] [] (mmc_power_up) from [] (mmc_start_host+0x44/0x6c)
[    2.722615] [] (mmc_start_host) from [] (mmc_add_host+0x58/0x7c)
[    2.730341] [] (mmc_add_host) from [] (sdhci_add_host+0x968/0xd94)
[    2.738240] [] (sdhci_add_host) from [] (sdhci_s3c_probe+0x354/0x52c)
[    2.746406] [] (sdhci_s3c_probe) from [] (platform_drv_probe+0x48/0xa4)
[    2.754733] [] (platform_drv_probe) from [] (driver_probe_device+0x13c/0x37c)
[    2.763585] [] (driver_probe_device) from [] (__driver_attach+0x94/0x98)
[    2.772003] [] (__driver_attach) from [] (bus_for_each_dev+0x54/0x88)
[    2.780163] [] (bus_for_each_dev) from [] (bus_add_driver+0xe4/0x200)
[    2.788322] [] (bus_add_driver) from [] (driver_register+0x78/0xf4)
[    2.796308] [] (driver_register) from [] (do_one_initcall+0xac/0x1f0)
[    2.804473] [] (do_one_initcall) from [] (kernel_init_freeable+0x10c/0x1d8)
[    2.813153] [] (kernel_init_freeable) from [] (kernel_init+0x28/0x108)
[    2.821398] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c)
[    2.828939] ---[ end trace 03cc00e539849d1f ]---

clk_set_rate() tries to take clk's prepare_lock mutex while being in atomic
context entered in sdhci_do_set_ios().

The solution is inspired by similar situation in sdhci_set_power() also called
from sdhci_do_set_ios():

                spin_unlock_irq(&host->lock);
                mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
                spin_lock_irq(&host->lock);

Note that since sdhci_s3c_set_clock() sets SDHCI_CLOCK_CARD_EN, proposed change
first resets this bit. It is reset anyway (by setting SDHCI_CLOCK_INT_EN bit
only) after call to clk_set_rate() in order to wait for the clock to stabilize
and is set again as soon as the clock becomes stable.

Signed-off-by: Paul Osmialowski 
Tested-by: Jaehoon Chung 
Acked-by: Jaehoon Chung 
Signed-off-by: Ulf Hansson 
Signed-off-by: Ben Hutchings

mmc: sdhci-s3c: Check if clk_set_rate() succeeds

2020-02-11T20:03:57+00:00

commit cd0cfdd2485e6252b3c69284bf09d06c4d303116 upstream.

It is possible that we may fail to set the clock rate, if we do so then
log the failure and don't bother reprogramming the IP.

Signed-off-by: Mark Brown 
Acked-by: Jaehoon Chung 
Signed-off-by: Ulf Hansson 
Signed-off-by: Ben Hutchings

mmc: mmc: fix switch timeout issue caused by jiffies precision

2020-01-11T02:04:57+00:00

commit 987aa5f8059613bf85cbb6f64ffbd34f5cb7a9d1 upstream.

with CONFIG_HZ=100, the precision of jiffies is 10ms, and the
generic_cmd6_time of some card is also 10ms. then, may be current
time is only 5ms, but already timed out caused by jiffies precision.

Signed-off-by: Chaotian Jing 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
Signed-off-by: Ben Hutchings

mmc: block: Allow more than 8 partitions per card

2020-01-11T02:04:49+00:00

commit 382c55f88ffeb218c446bf0c46d0fc25d2795fe2 upstream.

It is quite common for Android devices to utilize more
then 8 partitions on internal eMMC storage.

The vanilla kernel can support this via
CONFIG_MMC_BLOCK_MINORS, however that solution caps the
system to 256 minors total, which limits the number of
mmc cards the system can support.

This patch, which has been carried for quite awhile in
the AOSP common tree, provides an alternative solution
that doesn't seem to limit the total card count. So I
wanted to submit it for consideration upstream.

This patch sets the GENHD_FL_EXT_DEVT flag, which will
allocate minor number in major 259 for partitions past
disk->minors.

It also removes the use of disk_devt to determine devidx
from md->disk. md->disk->first_minor is always initialized
from devidx and can always be used to recover it.

Cc: Ulf Hansson 
Cc: Adrian Hunter 
Cc: Ben Hutchings 
Cc: Chuanxiao Dong 
Cc: Shawn Lin 
Cc: Austin S Hemmelgarn 
Cc: Arnd Bergmann 
Cc: Android Kernel Team 
Cc: linux-mmc@vger.kernel.org
Signed-off-by: Colin Cross 
[jstultz: Added context to commit message]
Signed-off-by: John Stultz 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings

mmc: core: fix using wrong io voltage if mmc_select_hs200 fails

2020-01-11T02:04:44+00:00

commit e51534c806609c806d81bfb034f02737461f855c upstream.

Currently MMC core will keep going if HS200/HS timing switch failed
with -EBADMSG error by the assumption that the old timing is still valid.

However, for mmc_select_hs200 case, the signal voltage may have already
been switched. If the timing switch failed, we should fall back to
the old voltage in case the card is continue run with legacy timing.

If fall back signal voltage failed, we explicitly report an EIO error
to force retry during the next power cycle.

Signed-off-by: Dong Aisheng 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
[bwh: Backported to 3.16:
 - Delete now-unused err label
 - Adjust context]
Signed-off-by: Ben Hutchings

mmc: core: shut up "voltage-ranges unspecified" pr_info()

2020-01-11T02:04:43+00:00

commit 10a16a01d8f72e80f4780e40cf3122f4caffa411 upstream.

Each time a driver such as sdhci-esdhc-imx is probed, we get a info
printk complaining that the DT voltage-ranges property has not been
specified.

However, the DT binding specifically says that the voltage-ranges
property is optional.  That means we should not be complaining that
DT hasn't specified this property: by indicating that it's optional,
it is valid not to have the property in DT.

Silence the warning if the property is missing.

Signed-off-by: Russell King 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
Signed-off-by: Ben Hutchings

mmc: sanitize 'bus width' in debug output

2020-01-11T02:04:43+00:00

commit ed9feec72fc1fa194ebfdb79e14561b35decce63 upstream.

The bus width is sometimes the actual bus width, and sometimes indices
to different arrays encoding the bus width. In my debugging case "2"
could mean 8-bit as well as 4-bit, which was extremly confusing. Let's
use the human-readable actual bus width in all places.

Signed-off-by: Wolfram Sang 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
Signed-off-by: Ben Hutchings

mmc: debugfs: Add a restriction to mmc debugfs clock setting

2020-01-11T02:04:42+00:00

commit e5905ff1281f0a0f5c9863c430ac1ed5faaf5707 upstream.

Clock frequency values written to an mmc host should not be less than
the minimum clock frequency which the mmc host supports.

Signed-off-by: Yuan Juntao 
Signed-off-by: Pawel Wodkowski 
Signed-off-by: Ulf Hansson 
Cc: Arnd Bergmann 
Signed-off-by: Ben Hutchings