linux-stable.git/drivers/mmc/host, branch v5.10

mmc: mediatek: mark PM functions as __maybe_unused

2020-12-04T14:35:54+00:00

The #ifdef check for the suspend/resume functions is wrong:

drivers/mmc/host/mtk-sd.c:2765:12: error: unused function 'msdc_suspend' [-Werror,-Wunused-function]
static int msdc_suspend(struct device *dev)
drivers/mmc/host/mtk-sd.c:2779:12: error: unused function 'msdc_resume' [-Werror,-Wunused-function]
static int msdc_resume(struct device *dev)

Remove the #ifdef and mark all four as __maybe_unused to aovid the
problem.

Fixes: c0a2074ac575 ("mmc: mediatek: Fix system suspend/resume support for CQHCI")
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann 
Link: https://lore.kernel.org/r/20201203222922.1067522-1-arnd@kernel.org
Signed-off-by: Ulf Hansson

mmc: tmio: improve bringing HW to a sane state with MMC_POWER_OFF

2020-12-04T11:33:59+00:00

Further testing of error cases revealed that downgrade is not enough, so
we need to reset the SCC which is done by calling the custom reset
function. This reset function can distinguish between the various SDHI
variants, so protecting the call with MIN_RCAR2 is enough here.

Fixes: 24ce2d7b8bea ("mmc: tmio: bring tuning HW to a sane state with MMC_POWER_OFF")
Reported-by: Yoshihiro Shimoda 
Signed-off-by: Wolfram Sang 
Reviewed-by: Yoshihiro Shimoda 
Tested-by: Yoshihiro Shimoda 
Link: https://lore.kernel.org/r/20201125204953.3344-1-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson

mmc: sdhci-of-arasan: Fix clock registration error for Keem Bay SOC

2020-11-24T10:28:12+00:00

The commit 16ada730a759 ("mmc: sdhci-of-arasan: Modify clock operations
handling") introduced support for platform specific clock operations.
Around the same point in time the commit 36c6aadaae86 ("mmc:
sdhci-of-arasan: Add support for Intel Keem Bay") was also  merged.
Unfortunate it was not really tested on top of the previously mentioned
commit, which causes clock registration failures for Keem Bay SOC devices.

Let's fix this, by properly declaring the clock operation for Keem Bay SOC
devices.

Fixes: 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay")
Signed-off-by: Muhammad Husaini Zulkifli 
Reviewed-by: Adrian Hunter 
Link: https://lore.kernel.org/r/20201118120120.24908-2-muhammad.husaini.zulkifli@intel.com
Cc: stable@vger.kernel.org
Signed-off-by: Ulf Hansson

mmc: mediatek: Extend recheck_sdio_irq fix to more variants

2020-11-24T10:27:38+00:00

The SDIO recheck fix is required for more of the supported variants. Let's
add it to those that needs it.

Reported-by: Fabien Parent 
Reported-by: Mattijs Korpershoek 
Signed-off-by: Yong Mao 
Link: https://lore.kernel.org/r/20201119030237.9414-1-yong.mao@mediatek.com
Fixes: 9e2582e57407 ("mmc: mediatek: fix SDIO irq issue")
Cc: stable@vger.kernel.org
[Ulf: Clarified commitmsg ]
Signed-off-by: Ulf Hansson

mmc: mediatek: Fix system suspend/resume support for CQHCI

2020-11-23T13:42:56+00:00

Before we got these errors on MT8192 platform:
[   59.153891] Restarting tasks ...
[   59.154540] done.
[   59.159175] PM: suspend exit
[   59.218724] mtk-msdc 11f60000.mmc: phase: [map:fffffffe] [maxlen:31]
[final:16]
[  119.776083] mmc0: cqhci: timeout for tag 9
[  119.780196] mmc0: cqhci: ============ CQHCI REGISTER DUMP ===========
[  119.786709] mmc0: cqhci: Caps:      0x100020b6 | Version:  0x00000510
[  119.793225] mmc0: cqhci: Config:    0x00000101 | Control:  0x00000000
[  119.799706] mmc0: cqhci: Int stat:  0x00000000 | Int enab: 0x00000000
[  119.806177] mmc0: cqhci: Int sig:   0x00000000 | Int Coal: 0x00000000
[  119.812670] mmc0: cqhci: TDL base:  0x00000000 | TDL up32: 0x00000000
[  119.819149] mmc0: cqhci: Doorbell:  0x003ffc00 | TCN:      0x00000200
[  119.825656] mmc0: cqhci: Dev queue: 0x00000000 | Dev Pend: 0x00000000
[  119.832155] mmc0: cqhci: Task clr:  0x00000000 | SSC1:     0x00001000
[  119.838627] mmc0: cqhci: SSC2:      0x00000000 | DCMD rsp: 0x00000000
[  119.845174] mmc0: cqhci: RED mask:  0xfdf9a080 | TERRI:    0x0000891c
[  119.851654] mmc0: cqhci: Resp idx:  0x00000000 | Resp arg: 0x00000000
[  119.865773] mmc0: cqhci: : ===========================================
[  119.872358] mmc0: running CQE recovery
From these logs, we found TDL base was back to the default value.

After suspend, the mmc host is powered off by HW, and bring CQE register
to the default value, so we add system suspend/resume interface, then bring
CQE to deactivated state before suspend, it will be enabled by CQE first
request after resume.

Signed-off-by: Wenbin Mei 
Link: https://lore.kernel.org/r/20201118063405.24906-1-wenbin.mei@mediatek.com
Fixes: 88bd652b3c74 ("mmc: mediatek: command queue support")
Cc: stable@vger.kernel.org
[Ulf: Renamed functions]
Signed-off-by: Ulf Hansson

mmc: sdhci-of-arasan: Issue DLL reset explicitly

2020-11-17T11:44:44+00:00

In the current implementation DLL reset will be issued for
each ITAP and OTAP setting inside ATF, this is creating issues
in some scenarios and this sequence is not inline with the TRM.
To fix the issue, DLL reset should be removed from the ATF and
host driver will request it explicitly.
This patch update host driver to explicitly request for DLL reset
before ITAP (assert DLL) and after OTAP (release DLL) settings.

Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup")
Signed-off-by: Sai Krishna Potthuri 
Signed-off-by: Manish Narani 
Acked-by: Michal Simek 
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1605515565-117562-4-git-send-email-manish.narani@xilinx.com
Signed-off-by: Ulf Hansson

mmc: sdhci-of-arasan: Use Mask writes for Tap delays

2020-11-17T11:44:40+00:00

Mask the ITAP and OTAP delay bits before updating with the new
tap value for Versal platform.

Fixes: 1a470721c8f5 ("sdhci: arasan: Add support for Versal Tap Delays")
Signed-off-by: Sai Krishna Potthuri 
Signed-off-by: Manish Narani 
Acked-by: Michal Simek 
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1605515565-117562-3-git-send-email-manish.narani@xilinx.com
Signed-off-by: Ulf Hansson

mmc: sdhci-of-arasan: Allow configuring zero tap values

2020-11-17T11:43:47+00:00

Allow configuring the Output and Input tap values with zero to avoid
failures in some cases (one of them is SD boot mode) where the output
and input tap values may be already set to non-zero.

Fixes: a5c8b2ae2e51 ("mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup")
Signed-off-by: Sai Krishna Potthuri 
Signed-off-by: Manish Narani 
Acked-by: Michal Simek 
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1605515565-117562-2-git-send-email-manish.narani@xilinx.com
Signed-off-by: Ulf Hansson

mmc: sdhci-pci: Prefer SDR25 timing for High Speed mode for BYT-based Intel controllers

2020-11-17T11:33:06+00:00

A UHS setting of SDR25 can give better results for High Speed mode.
This is because there is no setting corresponding to high speed.  Currently
SDHCI sets no value, which means zero which is also the setting for SDR12.
There was an attempt to change this in sdhci.c but it caused problems for
some drivers, so it was reverted and the change was made to sdhci-brcmstb
in commit 2fefc7c5f7d16e ("mmc: sdhci-brcmstb: Fix incorrect switch to HS
mode").  Several other drivers also do this.

Signed-off-by: Adrian Hunter 
Cc: stable@vger.kernel.org # v5.4+
Link: https://lore.kernel.org/r/20201112133656.20317-1-adrian.hunter@intel.com
Signed-off-by: Ulf Hansson

Revert "mmc: renesas_sdhi: workaround a regression when reinserting SD cards"

2020-11-10T12:58:01+00:00

This reverts commit db1af1e9712920f47b5dc6a995fca3eec05ea85e. It was
only a workaround to hide a regression. We now have proper fixes.

Signed-off-by: Wolfram Sang 
Tested-by: Niklas Söderlund 
Reviewed-by: Yoshihiro Shimoda 
Tested-by: Yoshihiro Shimoda 
Link: https://lore.kernel.org/r/20201106072549.1495-4-wsa+renesas@sang-engineering.com
Signed-off-by: Ulf Hansson