linux-stable.git/drivers/mmc/host, branch v4.0.2

mmc: sunxi: Use devm_reset_control_get_optional() for reset control

2015-05-06T20:03:43+00:00

commit 9e71c589e44ddf2b86f361c81e360c6b0d0354b1 upstream.

The reset control for the sunxi mmc controller is optional. Some
newer platforms (sun6i, sun8i, sun9i) have it, while older ones
(sun4i, sun5i, sun7i) don't.

Use the properly stubbed _optional version so the driver does not
fail to compile when RESET_CONTROLLER=n.

This patch also adds a check for deferred probing on the reset
control.

Signed-off-by: Chen-Yu Tsai 
Acked-by: David Lanzendörfer 
Signed-off-by: Ulf Hansson 
Signed-off-by: Greg Kroah-Hartman

mmc: tmio: Remove bogus un-initialization in tmio_mmc_host_free()

2015-05-06T20:03:43+00:00

commit 13a6a2ed1f5e77ae47c2b1a8e3bf22b2fa2d56ba upstream.

If CONFIG_DEBUG_SLAB=y:

    sh_mobile_sdhi ee100000.sd: Got CD GPIO
    sh_mobile_sdhi ee100000.sd: Got WP GPIO
    platform ee100000.sd: Driver sh_mobile_sdhi requests probe deferral
    ...
    Slab corruption (Not tainted): kmalloc-1024 start=ed8b3c00, len=1024
    2d0: 00 00 00 00 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  ....kkkkkkkkkkkk
    Prev obj: start=ed8b3800, len=1024
    000: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk
    010: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b  kkkkkkkkkkkkkkkk

Struct tmio_mmc_host is embedded inside struct mmc_host, and thus is
freed by the call to mmc_free_host(). Hence it must not be written to
afterwards, as that will corrupt freed (and perhaps already reused)
memory.

Fixes: 94b110aff8679b14 ("mmc: tmio: add tmio_mmc_host_alloc/free()")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Ulf Hansson 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux

2015-02-21T20:30:30+00:00

Pull clock framework updates from Mike Turquette:
 "The clock framework changes contain the usual driver additions,
  enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based
  devices.

  Additionally the framework core underwent a bit of surgery with two
  major changes:

   - The boundary between the clock core and clock providers (e.g clock
     drivers) is now more well defined with dedicated provider helper
     functions.  struct clk no longer maps 1:1 with the hardware clock
     but is a true per-user cookie which helps us tracker users of
     hardware clocks and debug bad behavior.

   - The addition of rate constraints for clocks.  Rate ranges are now
     supported which are analogous to the voltage ranges in the
     regulator framework.

  Unfortunately these changes to the core created some breakeage.  We
  think we fixed it all up but for this reason there are lots of last
  minute commits trying to undo the damage"

* tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits)
  clk: Only recalculate the rate if needed
  Revert "clk: mxs: Fix invalid 32-bit access to frac registers"
  clk: qoriq: Add support for the platform PLL
  powerpc/corenet: Enable CLK_QORIQ
  clk: Replace explicit clk assignment with __clk_hw_set_clk
  clk: Add __clk_hw_set_clk helper function
  clk: Don't dereference parent clock if is NULL
  MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr
  clkdev: Always allocate a struct clk and call __clk_get() w/ CCF
  clk: shmobile: div6: Avoid division by zero in .round_rate()
  clk: mxs: Fix invalid 32-bit access to frac registers
  clk: omap: compile legacy omap3 clocks conditionally
  clkdev: Export clk_register_clkdev
  clk: Add rate constraints to clocks
  clk: remove clk-private.h
  pci: xgene: do not use clk-private.h
  arm: omap2+ remove dead clock code
  clk: Make clk API return per-user struct clk instances
  clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
  clk: tegra: Add support for the Tegra132 CAR IP block
  ...

mmc: sdhci-s3c: solve problem with sleeping in atomic context

2015-02-04T12:39:14+00:00

This change addresses following problem:

[    2.560726] ------------[ cut here ]------------
[    2.565341] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2744 lockdep_trace_alloc+0xec/0x118()
[    2.574439] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags))
[    2.579821] Modules linked in:
[    2.583038] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G        W      3.18.0-next-20141216-00002-g4ff197fc1902-dirty #1318
[    2.593796] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[    2.599892] [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[    2.607612] [] (show_stack) from [] (dump_stack+0x70/0xbc)
[    2.614822] [] (dump_stack) from [] (warn_slowpath_common+0x74/0xb0)
[    2.622885] [] (warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
[    2.631569] [] (warn_slowpath_fmt) from [] (lockdep_trace_alloc+0xec/0x118)
[    2.640246] [] (lockdep_trace_alloc) from [] (__kmalloc+0x3c/0x1cc)
[    2.648240] [] (__kmalloc) from [] (clk_fetch_parent_index+0xb8/0xd4)
[    2.656390] [] (clk_fetch_parent_index) from [] (clk_calc_new_rates+0xe0/0x1fc)
[    2.665415] [] (clk_calc_new_rates) from [] (clk_calc_new_rates+0x1b4/0x1fc)
[    2.674181] [] (clk_calc_new_rates) from [] (clk_set_rate+0x50/0xc8)
[    2.682265] [] (clk_set_rate) from [] (sdhci_cmu_set_clock+0x68/0x16c)
[    2.690503] [] (sdhci_cmu_set_clock) from [] (sdhci_do_set_ios+0xf0/0x64c)
[    2.699095] [] (sdhci_do_set_ios) from [] (sdhci_set_ios+0x20/0x2c)
[    2.707080] [] (sdhci_set_ios) from [] (mmc_power_up+0x118/0x1fc)
[    2.714889] [] (mmc_power_up) from [] (mmc_start_host+0x44/0x6c)
[    2.722615] [] (mmc_start_host) from [] (mmc_add_host+0x58/0x7c)
[    2.730341] [] (mmc_add_host) from [] (sdhci_add_host+0x968/0xd94)
[    2.738240] [] (sdhci_add_host) from [] (sdhci_s3c_probe+0x354/0x52c)
[    2.746406] [] (sdhci_s3c_probe) from [] (platform_drv_probe+0x48/0xa4)
[    2.754733] [] (platform_drv_probe) from [] (driver_probe_device+0x13c/0x37c)
[    2.763585] [] (driver_probe_device) from [] (__driver_attach+0x94/0x98)
[    2.772003] [] (__driver_attach) from [] (bus_for_each_dev+0x54/0x88)
[    2.780163] [] (bus_for_each_dev) from [] (bus_add_driver+0xe4/0x200)
[    2.788322] [] (bus_add_driver) from [] (driver_register+0x78/0xf4)
[    2.796308] [] (driver_register) from [] (do_one_initcall+0xac/0x1f0)
[    2.804473] [] (do_one_initcall) from [] (kernel_init_freeable+0x10c/0x1d8)
[    2.813153] [] (kernel_init_freeable) from [] (kernel_init+0x28/0x108)
[    2.821398] [] (kernel_init) from [] (ret_from_fork+0x14/0x2c)
[    2.828939] ---[ end trace 03cc00e539849d1f ]---

clk_set_rate() tries to take clk's prepare_lock mutex while being in atomic
context entered in sdhci_do_set_ios().

The solution is inspired by similar situation in sdhci_set_power() also called
from sdhci_do_set_ios():

                spin_unlock_irq(&host->lock);
                mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
                spin_lock_irq(&host->lock);

Note that since sdhci_s3c_set_clock() sets SDHCI_CLOCK_CARD_EN, proposed change
first resets this bit. It is reset anyway (by setting SDHCI_CLOCK_INT_EN bit
only) after call to clk_set_rate() in order to wait for the clock to stabilize
and is set again as soon as the clock becomes stable.

Signed-off-by: Paul Osmialowski 
Tested-by: Jaehoon Chung 
Acked-by: Jaehoon Chung 
Signed-off-by: Ulf Hansson

mmc: moxart: fix probe logic

2015-02-04T08:42:29+00:00

Jonas Jensen wanted to submit a patch for these, but apparently
forgot about it. I stumbled over this symptom first:

drivers/built-in.o: In function `moxart_probe':
:(.text+0x2af128): undefined reference to `of_dma_request_slave_channel'

This is because of_dma_request_slave_channel is an internal helper
and not exported to loadable module. I'm changing the driver to
use dma_request_slave_channel_reason() instead.

Further problems from inspection:

* The remove function must not call kfree on the host pointer,
  because it is allocated together with the mmc_host.

* The clock is never released

* The dma_cap_mask_t is completely unused and can be removed

* deferred probing does not work if the dma driver is loaded
  after the mmc driver.

This patch should fix all of the above.

Signed-off-by: Arnd Bergmann 
Signed-off-by: Jonas Jensen 
Signed-off-by: Ulf Hansson

Merge branch 'clk-next' into v3.19-rc7

2015-02-02T22:59:38+00:00

mmc: Add hardware dependencies for sdhci-pxav3 and sdhci-pxav2

2015-01-30T10:44:42+00:00

I seem to understand that the sdhci-pxav3 and sdhci-pxav2 drivers are
only needed on the MMP architecture. So add a hardware dependency on
ARCH_MMP, so that other users don't get to build useless drivers.

Signed-off-by: Jean Delvare 
Cc: Chris Ball 
Cc: Ulf Hansson 
Cc: Eric Miao 
Acked-by: Haojian Zhuang 
Signed-off-by: Ulf Hansson

mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes

2015-01-29T12:08:46+00:00

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register.

This commit add the support of this register and for SDR50 or DDR50
mode use it as suggested by the erratum:
- Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not
inverted.
- Set the Sample FeedBack Clock field to 0x1

[gregory.clement@free-electrons.com: port from 3.10]

Signed-off-by: Gregory CLEMENT 
Signed-off-by: Ulf Hansson

mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ERR-7878951

2015-01-29T12:08:02+00:00

According to erratum 'ERR-7878951' Armada 38x SDHCI controller has
different capabilities than the ones shown in its registers:

- it doesn't support the voltage switching: it can work either with
  3.3V or 1.8V supply
- it doesn't support the SDR104 mode
- SDR50 mode doesn't need tuning

The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the
capabilities accordingly.

[gregory.clement@free-electrons.com: port from 3.10]

Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc:  # v3.15+

Signed-off-by: Gregory CLEMENT 
Signed-off-by: Ulf Hansson

mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavor

2015-01-29T12:07:41+00:00

According to erratum 'FE-2946959' both SDR50 and DDR50 modes require
specific clock adjustments in SDIO3 Configuration register. However,
this register was not part of the device tree binding. Even if the
binding can (and will) be extended we still need handling the case
where this register was not available. In this case we use the
SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities.

This commit is based on the work done by Marcin Wojtas

Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller")
Cc:  # v3.15+
Signed-off-by: Gregory CLEMENT 
Signed-off-by: Marcin Wojtas 
Signed-off-by: Ulf Hansson