linux-stable.git/drivers/memory, branch linux-5.6.y Linux kernel stable tree memory: tegra: Correct debugfs clk rate-range on Tegra124 2020-04-23T08:38:02+00:00 Dmitry Osipenko digetx@gmail.com 2020-02-24T23:58:36+00:00 e13b8ceb4b43c3b8b6bb936adb2d6a6697210865 [ Upstream commit 141267bffd1dc19a76e4d50e3e4829f85a806875 ] Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 6b9acd935546 ("memory: tegra: Refashion EMC debugfs interface on Tegra124") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 141267bffd1dc19a76e4d50e3e4829f85a806875 ]

Correctly set clk rate-range if number of available timings is zero.
This fixes noisy "invalid range [4294967295, 0]" error messages during
boot.

Fixes: 6b9acd935546 ("memory: tegra: Refashion EMC debugfs interface on Tegra124")
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
memory: tegra: Correct debugfs clk rate-range on Tegra30 2020-04-23T08:38:02+00:00 Dmitry Osipenko digetx@gmail.com 2020-02-24T23:58:35+00:00 8a2864d65873300e9132f1e12ee7745bb5075e1b [ Upstream commit a53670e1a734ba56fac84cf2b93b838bd4a6b835 ] Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit a53670e1a734ba56fac84cf2b93b838bd4a6b835 ]

Correctly set clk rate-range if number of available timings is zero.
This fixes noisy "invalid range [4294967295, 0]" error messages during
boot.

Fixes: 8cee32b40040 ("memory: tegra: Implement EMC debugfs interface on Tegra30")
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
memory: tegra: Correct debugfs clk rate-range on Tegra20 2020-04-23T08:38:02+00:00 Dmitry Osipenko digetx@gmail.com 2020-02-24T23:58:34+00:00 58db3e735afeeb2d830516449d45edd198eac174 [ Upstream commit 2243af41115d0e36e6414df6dd2a0386e022d9f8 ] Correctly set clk rate-range if number of available timings is zero. This fixes noisy "invalid range [4294967295, 0]" error messages during boot. Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org> 
[ Upstream commit 2243af41115d0e36e6414df6dd2a0386e022d9f8 ]

Correctly set clk rate-range if number of available timings is zero.
This fixes noisy "invalid range [4294967295, 0]" error messages during
boot.

Fixes: 8209eefa3d37 ("memory: tegra: Implement EMC debugfs interface on Tegra20")
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into arm/drivers 2020-01-16T18:45:44+00:00 Olof Johansson olof@lixom.net 2020-01-16T18:45:42+00:00 c7ce73eb018566222542adfb21f18961d0009286 mvebu drivers for 5.6 (part 1) - Various cleanup on the following drivers: - Turris Mox rWTM firmware - Moxtet bus - Armada 37xx rWTM mailbox - Marvell EBU Device Bus * tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu: mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource memory: mvebu-devbus: convert to devm_platform_ioremap_resource bus: moxtet: declare moxtet_bus_type as static firmware: turris-mox-rwtm: small white space cleanup Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net> 
mvebu drivers for 5.6 (part 1)

 - Various cleanup on the following drivers:
   - Turris Mox rWTM firmware
   - Moxtet bus
   - Armada 37xx rWTM mailbox
   - Marvell EBU Device Bus

* tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu:
  mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource
  memory: mvebu-devbus: convert to devm_platform_ioremap_resource
  bus: moxtet: declare moxtet_bus_type as static
  firmware: turris-mox-rwtm: small white space cleanup

Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers 2020-01-16T18:41:48+00:00 Olof Johansson olof@lixom.net 2020-01-16T18:41:47+00:00 083b4db857310ad269fc49e0019dd0f8fee305d3 memory: tegra: Changes for v5.6-rc1 This adds a couple of fixes for the Tegra30 EMC frequency scaling code and adds support for EMC frequency scaling on Tegra186 and later. * tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence memory: tegra: Correct reset value of xusb_hostr memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later memory: tegra: Add system sleep support memory: tegra: Extract memory client SID programming memory: tegra: Add per-SoC data for Tegra186 memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 memory: tegra: Implement EMC debugfs interface on Tegra30 memory: tegra: Implement EMC debugfs interface on Tegra20 memory: tegra: Refashion EMC debugfs interface on Tegra124 Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net> 
memory: tegra: Changes for v5.6-rc1

This adds a couple of fixes for the Tegra30 EMC frequency scaling code
and adds support for EMC frequency scaling on Tegra186 and later.

* tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  memory: tegra30-emc: Correct error message for timed out auto calibration
  memory: tegra30-emc: Firm up hardware programming sequence
  memory: tegra30-emc: Firm up suspend/resume sequence
  memory: tegra: Correct reset value of xusb_hostr
  memory: tegra: Add support for the Tegra194 memory controller
  memory: tegra: Only include support for enabled SoCs
  memory: tegra: Support DVFS on Tegra186 and later
  memory: tegra: Add system sleep support
  memory: tegra: Extract memory client SID programming
  memory: tegra: Add per-SoC data for Tegra186
  memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186
  memory: tegra: Implement EMC debugfs interface on Tegra30
  memory: tegra: Implement EMC debugfs interface on Tegra20
  memory: tegra: Refashion EMC debugfs interface on Tegra124

Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
memory: tegra30-emc: Correct error message for timed out auto calibration 2020-01-10T14:48:48+00:00 Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:49+00:00 5e5eca6644873da93f5a32904f43220380f34e88 The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
The code waits for auto calibration to be finished and not to be disabled.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra30-emc: Firm up hardware programming sequence 2020-01-10T14:48:40+00:00 Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:48+00:00 0f8bb9da5aee80d8d1b716e0fc5441575ff0ef21 Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Previously there was a problem where a late handshake handling caused
a memory corruption, this problem was resolved by issuing calibration
command right after changing the timing, but looks like the solution
wasn't entirely correct since calibration interval could be disabled as
well. Now programming sequence is completed immediately after receiving
handshake from CaR, without potentially long delays and in accordance to
the TRM's programming guide.

Secondly, the TRM's programming guide suggests to flush EMC writes by
reading any *MC* register before doing CaR changes. This is also addressed
now.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra30-emc: Firm up suspend/resume sequence 2020-01-10T14:47:18+00:00 Dmitry Osipenko digetx@gmail.com 2019-12-20T02:08:47+00:00 51bb73f93410a30550641f69d14cfb7b43fd2da1 The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
The current code doesn't prevent race conditions of suspend/resume vs CCF.
Let's take exclusive control over the EMC clock during suspend in a way
that is free from race conditions.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Correct reset value of xusb_hostr 2020-01-10T14:34:06+00:00 Nicolin Chen nicoleotsuka@gmail.com 2019-12-20T00:29:11+00:00 5f5636ef1de9174db8333787086a0e105938a2c5 According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr
field (bit [7:0]) should be 0x7a. So this patch simply corrects it.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add support for the Tegra194 memory controller 2020-01-09T18:38:38+00:00 Thierry Reding treding@nvidia.com 2019-12-22T14:10:32+00:00 a127e690b051df030f5ad2e28b14e8c3a624c145 The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <treding@nvidia.com> 
The memory and external memory controllers on Tegra194 are very similar
to their predecessors from Tegra186. Add the necessary SoC-specific data
to support the newer versions.

Signed-off-by: Thierry Reding <treding@nvidia.com>