linux-stable.git/drivers/memory/tegra/mc.h, branch linux-5.6.y

memory: tegra: Consolidate registers definition into common header

2019-11-11T13:55:27+00:00

The Memory Controller registers definition is sparse and duplicated,
let's consolidate everything into a common place for consistency.

Acked-by: Peter De Schrijver 
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra: Ensure timing control debug features are disabled

2019-11-11T13:55:27+00:00

Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.

Acked-by: Peter De Schrijver 
Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra: Introduce Tegra30 EMC driver

2019-11-11T13:55:27+00:00

Introduce driver for the External Memory Controller (EMC) found on Tegra30
chips, it controls the external DRAM on the board. The purpose of this
driver is to program memory timing for external memory on the EMC clock
rate change.

Acked-by: Peter De Schrijver 
Signed-off-by: Dmitry Osipenko 
Tested-by: Peter Geis 
Signed-off-by: Thierry Reding

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55+00:00

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Enrico Weigelt 
Reviewed-by: Kate Stewart 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman

memory: tegra: Properly spell "tegra"

2019-04-11T15:58:41+00:00

Rename all occurrences of "terga" to "tegra". It's an easy typo to make
and a difficult one to spot.

Reviewed-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra: Use relaxed versions of readl/writel

2019-01-16T12:54:12+00:00

There is no need for inserting of memory barriers to access registers of
Memory Controller. Hence use the relaxed versions of the accessors.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Adapt to Tegra20 device-tree binding changes

2019-01-16T12:54:11+00:00

The tegra20-mc device-tree binding has been changed, GART has been
squashed into Memory Controller and now the clock property is mandatory
for Tegra20, the DT compatible has been changed as well. Adapt driver to
the DT changes.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Signed-off-by: Joerg Roedel

memory: tegra: Introduce memory client hot reset

2018-04-30T08:12:21+00:00

In order to reset busy HW properly, memory controller needs to be
involved, otherwise it is possible to get corrupted memory or hang machine
if HW was reset during DMA. Introduce memory client 'hot reset' that will
be used for resetting of busy HW.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra: Squash tegra20-mc into common tegra-mc driver

2018-04-30T08:10:00+00:00

Tegra30+ has some minor differences in registers / bits layout compared
to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver
in a preparation for the upcoming MC hot reset controls implementation,
avoiding code duplication.

Note that this currently doesn't report the value of MC_GART_ERROR_REQ
because it is located within the GART register area and cannot be safely
accessed from the MC driver (this happens to work only by accident). The
proper solution is to integrate the GART driver with the MC driver, much
like is done for the Tegra SMMU, but that is an invasive change and will
be part of a separate patch series.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

memory: tegra: Apply interrupts mask per SoC

2018-04-27T09:23:04+00:00

Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding