linux-stable.git/drivers/irqchip, branch v5.12.2

irqchip/ingenic: Add support for the JZ4760

2021-03-09T08:45:17+00:00

Add support for the interrupt controller found in the JZ4760 SoC, which
works exactly like the one in the JZ4770.

Signed-off-by: Paul Cercueil 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210307172014.73481-2-paul@crapouillou.net

irqchip: Do not blindly select CONFIG_GENERIC_IRQ_MULTI_HANDLER

2021-03-08T20:18:41+00:00

Implementing CONFIG_GENERIC_IRQ_MULTI_HANDLER is a decision that is
made at the architecture level, and shouldn't involve the irqchip
at all (we even provide a fallback helper when the option isn't
selected).

Drop all instances of such selection from non-arch code.

Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210217142800.2547737-1-maz@kernel.org
Signed-off-by: Mark Rutland 
Tested-by: Hector Martin 
Cc: Catalin Marinas 
Cc: James Morse 
Cc: Thomas Gleixner 
Cc: Will Deacon 
Signed-off-by: Marc Zyngier

Merge tag 'irqchip-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

2021-02-15T14:41:56+00:00

Pull irqchip updates from Marc Zyngier

 - New driver for the MIPS-based Realtek RTL838x/RTL839x SoC
 - Conversion of the sun6i-r support code to a hierarchical setup
 - Fix wake-up interrupts for the ls-extirq driver
 - Fix MSI allocation for the loongson-pch-msi driver
 - Add compatible strings for new Qualcomm SoCs
 - Tidy up a few Kconfig entries (IMX, CSKY)
 - Spelling phyksiz
 - Remove the sirfsoc and tango drivers

Link: https://lore.kernel.org/r/20210214124015.3333457-1-maz@kernel.org

irqchip/imx: IMX_INTMUX should not default to y, unconditionally

2021-02-14T12:01:16+00:00

Merely enabling CONFIG_COMPILE_TEST should not enable additional code.
To fix this, restrict the automatic enabling of IMX_INTMUX to ARCH_MXC,
and ask the user in case of compile-testing.

Fixes: 66968d7dfc3f5451 ("irqchip: Add COMPILE_TEST support for IMX_INTMUX")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210208145605.422943-1-geert+renesas@glider.be

irqchip/loongson-pch-msi: Use bitmap_zalloc() to allocate bitmap

2021-02-09T10:41:40+00:00

Currently we use bitmap_alloc() to allocate msi bitmap which should be
initialized with zero. This is obviously wrong but it works because msi
can fallback to legacy interrupt mode. So use bitmap_zalloc() instead.

Fixes: 632dcc2c75ef6de3272aa ("irqchip: Add Loongson PCH MSI controller")
Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210209071051.2078435-1-chenhuacai@loongson.cn

irqchip/csky-mpintc: Prevent selection on unsupported platforms

2021-02-04T10:37:28+00:00

The irq-csky-mpintc driver is only supported on CPU_CK860 and
it will generate a compilation error when selected with CPU_CK610.

As it is already selected directly in the architecture Kconfig,
drop the option to select it manually.

Signed-off-by: Guo Ren 
[maz: rewrote commit message]
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210204074609.3553018-1-guoren@kernel.org

irqchip: Add support for Realtek RTL838x/RTL839x interrupt controller

2021-02-04T10:36:15+00:00

This is a standard IRQ driver with only status and mask registers.

The mapping from SoC interrupts (18-31) to MIPS core interrupts is
done via an interrupt-map in device tree.

Signed-off-by: Bert Vermeulen 
Signed-off-by: Birger Koblitz 
Acked-by: John Crispin 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210122204224.509124-3-bert@biot.com

irqchip/ls-extirq: add IRQCHIP_SKIP_SET_WAKE to the irqchip flags

2021-01-29T11:06:38+00:00

The ls-extirq driver doesn't implement the irq_set_wake()
callback, while being wake-up capable. This results in
ugly behaviours across suspend/resume cycles.

Advertise this by adding IRQCHIP_SKIP_SET_WAKE to
the irqchip flags

Fixes: b16a1caf4686 ("irqchip/ls-extirq: Add LS1043A, LS1088A external interrupt support")
Signed-off-by: Biwen Li 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210129095034.33821-1-biwen.li@oss.nxp.com

irqchip/sun6i-r: Add wakeup support

2021-01-21T20:21:49+00:00

Maintain bitmaps of wake-enabled IRQs and mux inputs, and program them
to the hardware during the syscore phase of suspend and shutdown. Then
restore the original set of enabled IRQs (only the NMI) during resume.

This serves two purposes. First, it lets power management firmware
running on the ARISC coprocessor know which wakeup sources Linux wants
to have enabled. That way, it can avoid turning them off when it shuts
down the remainder of the clock tree. Second, it preconfigures the
coprocessor's interrupt controller, so the firmware's wakeup logic
is as simple as waiting for an interrupt to arrive.

The suspend/resume logic is not conditional on PM_SLEEP because it is
identical to the init/shutdown logic. Wake IRQs may be enabled during
shutdown to allow powering the board back on. As an example, see
commit a5c5e50cce9d ("Input: gpio-keys - add shutdown callback").

Acked-by: Maxime Ripard 
Signed-off-by: Samuel Holland 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210118055040.21910-5-samuel@sholland.org

irqchip/sun6i-r: Use a stacked irqchip driver

2021-01-21T20:21:49+00:00

The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
original sun4i interrupt controller than the sun7i/sun9i NMI controller.
It is used for two distinct purposes:
 - To control the trigger, latch, and mask for the NMI input pin
 - To provide the interrupt input for the ARISC coprocessor

As this interrupt controller is not documented, information about it
comes from vendor-provided firmware blobs and from experimentation.

Differences from the sun4i interrupt controller appear to be:
 - It only has one or two registers of each kind (max 32 or 64 IRQs)
 - Multiplexing logic is added to support additional inputs
 - There is no FIQ-related logic
 - There is no interrupt priority logic

In order to fulfill its two purposes, this hardware block combines four
types of IRQs. First, the NMI pin is routed to the "IRQ 0" input on this
chip, with a trigger type controlled by the NMI_CTRL_REG. The "IRQ 0
pending" output from this chip, if enabled, is then routed to a SPI IRQ
input on the GIC. In other words, bit 0 of IRQ_ENABLE_REG *does* affect
the NMI IRQ seen at the GIC.

The NMI is followed by a contiguous block of 15 "direct" (my name for
them) IRQ inputs that are connected in parallel to both R_INTC and the
GIC. Or in other words, these bits of IRQ_ENABLE_REG *do not* affect the
IRQs seen at the GIC.

Following the direct IRQs are the ARISC's copy of banked IRQs for shared
peripherals. These are not relevant to Linux. The remaining IRQs are
connected to a multiplexer and provide access to the first (up to) 128
SPIs from the ARISC. This range of SPIs overlaps with the direct IRQs.

Because of the 1:1 correspondence between R_INTC and GIC inputs, this is
a perfect scenario for using a stacked irqchip driver. We want to hook
into setting the NMI trigger type, but not actually handle any IRQ here.

To allow access to all multiplexed IRQs, this driver requires a new
binding where the interrupt number matches the GIC interrupt number.
(This moves the NMI from number 0 to 32 or 96, depending on the SoC.)
For simplicity, copy the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.

Since R_INTC is in the always-on power domain, and its output is visible
to the power management coprocessor, a stacked irqchip driver provides a
simple way to add wakeup support to any of its IRQs. That is the next
patch; for now, just the NMI is moved over.

This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").

Acked-by: Maxime Ripard 
Signed-off-by: Samuel Holland 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20210118055040.21910-4-samuel@sholland.org