linux-stable.git/drivers/irqchip, branch v4.3.3

irqchip/tegra: Propagate IRQ type setting to parent

2015-10-26T00:20:59+00:00

The LIC doesn't deal with the different types of interrupts itself
but needs to forward calls to set the appropriate type to its parent
IRQ controller.

Without this fix all IRQs routed through the LIC will stay at the
initial EDGE type, while most of them should actually be level triggered.

Fixes: 1eec582158e2 "irqchip: tegra: Add Tegra210 support"
Signed-off-by: Lucas Stach 
Cc: Stephen Warren 
Cc: Thierry Reding 
Cc: Alexandre Courbot 
Cc: Jason Cooper 
Cc: Marc Zyngier 
Cc:  # 4.1
Link: http://lkml.kernel.org/r/1445787552-13062-1-git-send-email-dev@lynxeye.de
Signed-off-by: Thomas Gleixner

irqchip/armada-370-xp: Fix regression by clearing IRQ_NOAUTOEN

2015-10-26T00:19:06+00:00

Commit d17cab4451df1 ("irqchip: Kill off set_irq_flags usage") changed
the code of armada_370_xp_mpic_irq_map() from using set_irq_flags() to
irq_set_probe().

While the commit log seems to imply that there are no functional
changes, there are indeed functional changes introduced by this
commit: the IRQ_NOAUTOEN flag is no longer cleared. This functional
change causes a regression on Armada XP, which no longer works
properly after suspend/resume because per-CPU interrupts remain
disabled.

Due to how the hardware registers work, the irq-armada-370-xp cannot
simply save/restore a bunch of registers at suspend/resume to make
sure that the interrupts remain in the same state after
resuming. Therefore, it relies on the kernel to say whether the
interrupt is disabled or not, using the irqd_irq_disabled()
function. This was all working fine while the IRQ_NOAUTOEN flag was
cleared.

With the change introduced by Rob Herring in d17cab4451df1, the
IRQ_NOAUTOEN flag is now set for all interrupts. irqd_irq_disabled()
returns false for per-CPU interrupts, and therefore our per-CPU
interrupts are no longer re-enabled after resume.

This commit works around this problem by clearing again the
IRQ_NOAUTOEN flags, so that we are back to the situation we had before
commit d17cab4451df1. This work around is proposed as a minimal fix
for the problem, while a better long-term solution is being worked on.

Fixes: d17cab4451df1 "irqchip: Kill off set_irq_flags usage"
Signed-off-by: Thomas Petazzoni
Link: https://lkml.kernel.org/r/1445435295-19956-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
Signed-off-by: Thomas Gleixner

Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2015-10-04T10:40:09+00:00

Pull irq fixes from Thomas Gleixner:
 "This update contains:

   - Fix for a long standing race affecting /proc/irq/NNN

   - One line fix for ARM GICV3-ITS counting the wrong data

   - Warning silencing in ARM GICV3-ITS.  Another GCC trying to be
     overly clever issue"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3-its: Count additional LPIs for the aliased devices
  irqchip/gic-v3-its: Silence warning when its_lpi_alloc_chunks gets inlined
  genirq: Fix race in register_irq_proc()

irqchip/gic-v3-its: Count additional LPIs for the aliased devices

2015-10-02T18:51:41+00:00

When configuring the interrupt mapping for a new device, we
iterate over all the possible aliases to account for their
maximum MSI allocation. This was introduced by e8137f4f5088
("irqchip: gicv3-its: Iterate over PCI aliases to generate ITS configuration").

Turns out that the code doing that is a bit braindead, and repeatedly
accounts for the same device over and over.

Fix this by counting the actual alias that is passed to us by the
core code.

Signed-off-by: Marc Zyngier 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Alex Shi 
Cc: Ard Biesheuvel 
Cc: David Daney 
Cc: Jason Cooper 
Link: http://lkml.kernel.org/r/1443800646-8074-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner

irqchip/gic-v3-its: Silence warning when its_lpi_alloc_chunks gets inlined

2015-10-02T18:51:41+00:00

More agressive inlining in recent versions of GCC have uncovered
a new set of warnings:

 drivers/irqchip/irq-gic-v3-its.c: In function its_msi_prepare:
  drivers/irqchip/irq-gic-v3-its.c:1148:26: warning: lpi_base may be used
    uninitialized in this function [-Wmaybe-uninitialized]
     dev->event_map.lpi_base = lpi_base;
                          ^
 drivers/irqchip/irq-gic-v3-its.c:1116:6: note: lpi_base was declared here
  int lpi_base;
	      ^
 drivers/irqchip/irq-gic-v3-its.c:1149:25: warning: nr_lpis may be used
  uninitialized in this function [-Wmaybe-uninitialized]
   dev->event_map.nr_lpis = nr_lpis;
	                         ^
 drivers/irqchip/irq-gic-v3-its.c:1117:6: note: nr_lpis was declared here
  int nr_lpis;
	      ^
The warning is fairly benign (there is no code path that could
actually use uninitialized variables), but let's silence it anyway
by zeroing the variables on the error path.

Reported-by: Alex Shi 
Tested-by: Ard Biesheuvel 
Signed-off-by: Marc Zyngier 
Cc: linux-arm-kernel@lists.infradead.org
Cc: David Daney 
Cc: Jason Cooper 
Link: http://lkml.kernel.org/r/1443800646-8074-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2015-09-27T22:22:34+00:00

Pull MIPS fixes from Ralf Baechle:
 - Properly setup irq handling for ATH79 platforms
 - Fix bootmem mapstart calculation for contiguous maps
 - Handle little endian and older CPUs correct in BPF
 - Fix console for Fulong 2E systems
 - Handle FTLB correctly on R6 CPUs
 - Fixes for CM, GIC and MAAR support code

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Initialise MAARs on secondary CPUs
  MIPS: print MAAR configuration during boot
  MIPS: mm: compile maar_init unconditionally
  irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC.
  irqchip: mips-gic: Convert CPU numbers to VP IDs.
  MIPS: CM: Provide a function to map from CPU to VP ID.
  MIPS: Fix FTLB detection for R6
  MIPS: cpu-features: Add cpu_has_ftlb
  MIPS: ATH79: Add irq chip ar7240-misc-intc
  MIPS: ATH79: Set missing irq ack handler for ar7100-misc-intc irq chip
  MIPS: BPF: Fix build on pre-R2 little endian CPUs
  MIPS: BPF: Avoid unreachable code on little endian
  MIPS: bootmem: Fix mapstart calculation for contiguous maps
  MIPS: Fix console output for Fulong2e system

irqchip: mips-gic: Fix pending & mask reads for MIPS64 with 32b GIC.

2015-09-27T12:11:18+00:00

gic_handle_shared_int reads the GIC interrupt pending & mask registers
directly into a bitmap, which is defined as an array of unsigned longs.
The GIC pending registers may be 32 bits wide if the CM is older than
CM3, regardless of the bit width of the CPU, but for MIPS64 kernels
the unsigned longs in the bitmap will be 64 bits wide. In this case we
need to perform 2 x 32 bit reads per 64 bit unsigned long in order to
avoid missing interrupts.

Signed-off-by: Paul Burton 
Acked-by: Thomas Gleixner 
Cc: linux-mips@linux-mips.org
Cc: Marc Zyngier 
Cc: Jason Cooper 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11213/
Signed-off-by: Ralf Baechle

irqchip: mips-gic: Convert CPU numbers to VP IDs.

2015-09-27T12:11:17+00:00

Make use of the mips_cm_vp_id function to convert from Linux CPU numbers
to the VP IDs used by hardware, which are not identical in all systems.
Without doing so we map interrupts to incorrect VP(E)s.

Signed-off-by: Paul Burton 
Acked-by: Thomas Gleixner 
Cc: linux-mips@linux-mips.org
Cc: Paul Burton 
Cc: Marc Zyngier 
Cc: Jason Cooper 
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11212/
Signed-off-by: Ralf Baechle

irqchip/atmel-aic5: Use per chip mask caches in mask/unmask()

2015-09-22T13:55:51+00:00

When masking/unmasking interrupts, mask_cache is updated and used later
for suspend/resume. Unfortunately, it always was the mask_cache
associated with the first irq chip which was updated. So when performing
resume, only irqs 0-31 could be enabled.

Fixes: b1479ebb7720 ("irqchip: atmel-aic: Add atmel AIC/AIC5 drivers")
Signed-off-by: Ludovic Desroches 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: 
Cc: stable@vger.kernel.org #3.18
Link: http://lkml.kernel.org/r/1442843173-2390-1-git-send-email-ludovic.desroches@atmel.com
Signed-off-by: Thomas Gleixner

irqchip: Kill off set_irq_flags usage

2015-09-16T14:53:38+00:00

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.

Signed-off-by: Rob Herring 
Cc: linux-arm-kernel@lists.infradead.org
Cc: Russell King 
Cc: Jason Cooper 
Cc: Kukjin Kim 
Cc: Krzysztof Kozlowski 
Cc: Stephen Warren 
Cc: Lee Jones 
Cc: Alexander Shiyan 
Cc: Maxime Ripard 
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Link: http://lkml.kernel.org/r/1440889285-5637-3-git-send-email-robh@kernel.org
Signed-off-by: Thomas Gleixner