linux-stable.git/drivers/irqchip, branch linux-6.5.y

irqchip/sifive-plic: Fix syscore registration for multi-socket systems

2023-11-20T10:56:45+00:00

[ Upstream commit f99b926f6543faeadba1b4524d8dc9c102489135 ]

Multi-socket systems have a separate PLIC in each socket, so __plic_init()
is invoked for each PLIC. __plic_init() registers syscore operations, which
obviously fails on the second invocation.

Move it into the already existing condition for installing the CPU hotplug
state so it is only invoked once when the first PLIC is initialized.

[ tglx: Massaged changelog ]

Fixes: e80f0b6a2cf3 ("irqchip/irq-sifive-plic: Add syscore callbacks for hibernation")
Signed-off-by: Anup Patel 
Signed-off-by: Thomas Gleixner 
Link: https://lore.kernel.org/r/20231025142820.390238-4-apatel@ventanamicro.com
Signed-off-by: Sasha Levin

irqchip/stm32-exti: add missing DT IRQ flag translation

2023-11-08T13:08:56+00:00

[ Upstream commit 8554cba1d6dbd3c74e0549e28ddbaccbb1d6b30a ]

The STM32F4/7 EXTI driver was missing the xlate callback, so IRQ trigger
flags specified in the device tree were being ignored. This was
preventing the RTC alarm interrupt from working, because it must be set
to trigger on the rising edge to function correctly.

Signed-off-by: Ben Wolsieffer 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20231003162003.1649967-1-ben.wolsieffer@hefring.com
Signed-off-by: Sasha Levin

irqchip/riscv-intc: Mark all INTC nodes as initialized

2023-11-08T13:08:56+00:00

[ Upstream commit e13cd66bd821be417c498a34928652db4ac6b436 ]

The RISC-V INTC local interrupts are per-HART (or per-CPU) so we
create INTC IRQ domain only for the INTC node belonging to the boot
HART. This means only the boot HART INTC node will be marked as
initialized and other INTC nodes won't be marked which results
downstream interrupt controllers (such as PLIC, IMSIC and APLIC
direct-mode) not being probed due to missing device suppliers.

To address this issue, we mark all INTC node for which we don't
create IRQ domain as initialized.

Reported-by: Dmitry Dunaev 
Signed-off-by: Anup Patel 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20230926102801.1591126-1-dunaev@tecon.ru
Link: https://lore.kernel.org/r/20231003044403.1974628-4-apatel@ventanamicro.com
Signed-off-by: Sasha Levin

irqchip: renesas-rzg2l: Fix logic to clear TINT interrupt source

2023-10-19T21:10:57+00:00

commit 9b8df572ba3f4e544366196820a719a40774433e upstream.

The logic to clear the TINT interrupt source in rzg2l_irqc_irq_disable()
is wrong as the mask is correct only for LSB on the TSSR register.
This issue is found when testing with two TINT interrupt sources. So fix
the logic for all TINTs by using the macro TSSEL_SHIFT() to multiply
tssr_offset with 8.

Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
Signed-off-by: Biju Das 
Tested-by: Claudiu Beznea 
Reviewed-by: Geert Uytterhoeven 
Reviewed-by: Claudiu Beznea 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20230918122411.237635-2-biju.das.jz@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman

irqchip/loongson-eiointc: Fix return value checking of eiointc_index

2023-09-13T07:53:00+00:00

[ Upstream commit 2e99b73afde18853754c5fae8e8d1a66fe5e3f64 ]

Return value of function eiointc_index is int, however it is converted
into uint32_t and then compared smaller than zero, this will cause logic
problem.

Fixes: dd281e1a1a93 ("irqchip: Add Loongson Extended I/O interrupt controller support")
Signed-off-by: Bibo Mao 
Reviewed-by: Philippe Mathieu-Daudé 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20230811095805.2974722-2-maobibo@loongson.cn
Signed-off-by: Sasha Levin

Merge tag 'irq_urgent_for_v6.5_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2023-07-30T17:59:19+00:00

Pull irq fixes from Borislav Petkov:

 - Work around an erratum on GIC700, where a race between a CPU handling
   a wake-up interrupt, a change of affinity, and another CPU going to
   sleep can result in a lack of wake-up event on the next interrupt

 - Fix the locking required on a VPE for GICv4

 - Enable Rockchip 3588001 erratum workaround for RK3588S

 - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be the first
   CPU in the system

* tag 'irq_urgent_for_v6.5_rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/gic-v3: Workaround for GIC-700 erratum 2941627
  irqchip/gic-v3: Enable Rockchip 3588001 erratum workaround for RK3588S
  irqchip/gic-v4.1: Properly lock VPEs when doing a directLPI invalidation
  irq-bcm6345-l1: Do not assume a fixed block to cpu mapping

Merge tag 'irqchip-fixes-6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent

2023-07-24T08:27:43+00:00

Pull irqchip fixes from Marc Zyngier:

  - Work around an erratum on GIC700, where a race between a CPU
    handling a wake-up interrupt, a change of affinity, and another
    CPU going to sleep can result in a lack of wake-up event on the
    next interrupt.

  - Fix the locking required on a VPE for GICv4

  - Enable Rockchip 3588001 erratum workaround for RK3588S

  - Fix the irq-bcm6345-l1 assumtions of the boot CPU always be
    the first CPU in the system

Link: https://lore.kernel.org/lkml/20230717113857.304919-1-maz@kernel.org

irqchip/gic-v3: Workaround for GIC-700 erratum 2941627

2023-07-11T08:04:31+00:00

GIC700 erratum 2941627 may cause GIC-700 missing SPIs wake
requests when SPIs are deactivated while targeting a
sleeping CPU - ie a CPU for which the redistributor:

GICR_WAKER.ProcessorSleep == 1

This runtime situation can happen if an SPI that has been
activated on a core is retargeted to a different core, it
becomes pending and the target core subsequently enters a
power state quiescing the respective redistributor.

When this situation is hit, the de-activation carried out
on the core that activated the SPI (through either ICC_EOIR1_EL1
or ICC_DIR_EL1 register writes) does not trigger a wake
requests for the sleeping GIC redistributor even if the SPI
is pending.

Work around the erratum by de-activating the SPI using the
redistributor GICD_ICACTIVER register if the runtime
conditions require it (ie the IRQ was retargeted between
activation and de-activation).

Signed-off-by: Lorenzo Pieralisi 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20230704155034.148262-1-lpieralisi@kernel.org

irqchip/gic-v3: Enable Rockchip 3588001 erratum workaround for RK3588S

2023-07-03T18:48:04+00:00

Commit a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum
workaround") mentioned RK3588S (the slimmed down variant of RK3588)
being affected, but did not check for its compatible value. Thus the
quirk is not applied on RK3588S. Since the GIC ITS node got added to the
upstream DT, boards using RK3588S are no longer booting without this
quirk being applied.

Fixes: 06cdac8e8407 ("arm64: dts: rockchip: add GIC ITS support to rk3588")
Signed-off-by: Sebastian Reichel 
Signed-off-by: Marc Zyngier 
Link: https://lore.kernel.org/r/20230703164129.193991-1-sebastian.reichel@collabora.com

irqchip/gic-v4.1: Properly lock VPEs when doing a directLPI invalidation

2023-07-03T18:48:04+00:00

We normally rely on the irq_to_cpuid_[un]lock() primitives to make
sure nothing will change col->idx while performing a LPI invalidation.

However, these primitives do not cover VPE doorbells, and we have
some open-coded locking for that. Unfortunately, this locking is
pretty bogus.

Instead, extend the above primitives to cover VPE doorbells and
convert the whole thing to it.

Fixes: f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access")
Reported-by: Kunkun Jiang 
Signed-off-by: Marc Zyngier 
Cc: Zenghui Yu 
Cc: wanghaibin.wang@huawei.com
Tested-by: Kunkun Jiang 
Reviewed-by: Zenghui Yu 
Link: https://lore.kernel.org/r/20230617073242.3199746-1-maz@kernel.org