<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/drivers/interconnect/qcom, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>Merge tag 'icc-7.3-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next</title>
<updated>2026-08-19T07:55:37+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2026-08-19T07:55:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1f7267d8043e394933b0ed06070bfa7921d7c830'/>
<id>1f7267d8043e394933b0ed06070bfa7921d7c830</id>
<content type='text'>
Georgi writes:

This pull request contains the following interconnect updates for
the 7.3-rc1 merge window:

- New driver for Maili SoC
- Add support for QoS on the SC8280XP SoC
- Add support for QoS on the x1e80100 SoC
- Add EPSS L3 scaling support for Shikra SoC
- Add COMPILE_TEST support for some platforms
- Misc tiny improvements and fixes

Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;

* tag 'icc-7.3-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: Fix use after free in icc_get() and of_icc_get_by_index()
  interconnect: debugfs-client: add NULL check for platform_device_alloc
  interconnect: qcom: simplify allocation
  interconnect: qcom: add COMPILE_TEST
  interconnect: qcom: add Maili interconnect provider driver
  dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
  interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC
  dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC
  interconnect: qcom: x1e80100: enable QoS configuration
  dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS
  interconnect: qcom: sc8280xp: Enable QoS configuration
  dt-bindings: interconnect: qcom,sc8280xp-rpmh: Add reg and clocks for QoS
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Georgi writes:

This pull request contains the following interconnect updates for
the 7.3-rc1 merge window:

- New driver for Maili SoC
- Add support for QoS on the SC8280XP SoC
- Add support for QoS on the x1e80100 SoC
- Add EPSS L3 scaling support for Shikra SoC
- Add COMPILE_TEST support for some platforms
- Misc tiny improvements and fixes

Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;

* tag 'icc-7.3-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc:
  interconnect: Fix use after free in icc_get() and of_icc_get_by_index()
  interconnect: debugfs-client: add NULL check for platform_device_alloc
  interconnect: qcom: simplify allocation
  interconnect: qcom: add COMPILE_TEST
  interconnect: qcom: add Maili interconnect provider driver
  dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
  interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC
  dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC
  interconnect: qcom: x1e80100: enable QoS configuration
  dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS
  interconnect: qcom: sc8280xp: Enable QoS configuration
  dt-bindings: interconnect: qcom,sc8280xp-rpmh: Add reg and clocks for QoS
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'icc-misc' into icc-next</title>
<updated>2026-07-22T10:51:41+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>djakov@kernel.org</email>
</author>
<published>2026-07-22T10:51:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9621c81fd2eb7db4b647814b7b6e537744831e60'/>
<id>9621c81fd2eb7db4b647814b7b6e537744831e60</id>
<content type='text'>
* icc-misc
  interconnect: qcom: add COMPILE_TEST
  interconnect: qcom: simplify allocation
  interconnect: debugfs-client: add NULL check for platform_device_alloc
  interconnect: Fix use after free in icc_get() and of_icc_get_by_index()

Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* icc-misc
  interconnect: qcom: add COMPILE_TEST
  interconnect: qcom: simplify allocation
  interconnect: debugfs-client: add NULL check for platform_device_alloc
  interconnect: Fix use after free in icc_get() and of_icc_get_by_index()

Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'icc-maili' into icc-next</title>
<updated>2026-07-22T10:51:09+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>djakov@kernel.org</email>
</author>
<published>2026-07-22T10:51:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=07522964616d08b45eb9dc590fc9177e386d31cf'/>
<id>07522964616d08b45eb9dc590fc9177e386d31cf</id>
<content type='text'>
Add interconnect bindings and RPMh-based interconnect driver support for
the upcoming Qualcomm Maili SoC.

* icc-maili
  dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
  interconnect: qcom: add Maili interconnect provider driver

Link: https://patch.msgid.link/20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add interconnect bindings and RPMh-based interconnect driver support for
the upcoming Qualcomm Maili SoC.

* icc-maili
  dt-bindings: interconnect: qcom: document the RPMh Network-On-Chip interconnect in Maili SoC
  interconnect: qcom: add Maili interconnect provider driver

Link: https://patch.msgid.link/20260622-maili_icc-v2-0-18b5ac08c04f@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'icc-shikra' into icc-next</title>
<updated>2026-07-22T10:50:47+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>djakov@kernel.org</email>
</author>
<published>2026-07-22T10:50:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=d5aee2777edbc0835ed806a784c39197da724014'/>
<id>d5aee2777edbc0835ed806a784c39197da724014</id>
<content type='text'>
Add Epoch Subsystem (EPSS) L3 scaling support on Qualcomm Shikra SoC.
EPSS hardware on Shikra is similar to other SoCs but supports only twelve
L3 frequency entries (LUT). Reading the LUT beyond supported frequencies
can expose incorrect frequencies.
Introduce new compatible to represent this constrained variant of EPSS.

* icc-shikra
  dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC
  interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC

Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-0-3c2e0b796e78@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Epoch Subsystem (EPSS) L3 scaling support on Qualcomm Shikra SoC.
EPSS hardware on Shikra is similar to other SoCs but supports only twelve
L3 frequency entries (LUT). Reading the LUT beyond supported frequencies
can expose incorrect frequencies.
Introduce new compatible to represent this constrained variant of EPSS.

* icc-shikra
  dt-bindings: interconnect: qcom,osm-l3: Add EPSS L3 DT binding for Qualcomm Shikra SoC
  interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC

Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-0-3c2e0b796e78@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>interconnect: qcom: simplify allocation</title>
<updated>2026-07-22T09:14:24+00:00</updated>
<author>
<name>Rosen Penev</name>
<email>rosenp@gmail.com</email>
</author>
<published>2026-06-09T22:24:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=bd8a131fbe4989b8e57aa74fdc974900460ac387'/>
<id>bd8a131fbe4989b8e57aa74fdc974900460ac387</id>
<content type='text'>
Use a flexible array member to reduce allocation by 1.

Add __counted_by for extra runtime analysis. Move counting variable
assignment after allocation before any array access.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260609222454.37352-1-rosenp@gmail.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Use a flexible array member to reduce allocation by 1.

Add __counted_by for extra runtime analysis. Move counting variable
assignment after allocation before any array access.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260609222454.37352-1-rosenp@gmail.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>interconnect: qcom: add COMPILE_TEST</title>
<updated>2026-07-22T09:13:57+00:00</updated>
<author>
<name>Rosen Penev</name>
<email>rosenp@gmail.com</email>
</author>
<published>2026-06-08T05:05:42+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=c96fc14322cee45cdf751cb4ae62c9eab25bc643'/>
<id>c96fc14322cee45cdf751cb4ae62c9eab25bc643</id>
<content type='text'>
Allow non-ARM to build this.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260608050542.6167-1-rosenp@gmail.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow non-ARM to build this.

Signed-off-by: Rosen Penev &lt;rosenp@gmail.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260608050542.6167-1-rosenp@gmail.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>interconnect: qcom: add Maili interconnect provider driver</title>
<updated>2026-07-07T14:18:03+00:00</updated>
<author>
<name>Raviteja Laggyshetty</name>
<email>raviteja.laggyshetty@oss.qualcomm.com</email>
</author>
<published>2026-06-22T06:34:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=fb8190f09bffaac5005084cf665743aef199b01f'/>
<id>fb8190f09bffaac5005084cf665743aef199b01f</id>
<content type='text'>
Add driver for the Qualcomm interconnect buses found in Maili
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.

Co-developed-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260622-maili_icc-v2-2-18b5ac08c04f@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add driver for the Qualcomm interconnect buses found in Maili
based platforms. The topology consists of several NoCs that are
controlled by a remote processor that collects the aggregated
bandwidth for each master-slave pairs.

Co-developed-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260622-maili_icc-v2-2-18b5ac08c04f@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>interconnect: qcom: Add EPSS L3 scaling support for Shikra SoC</title>
<updated>2026-07-07T14:06:52+00:00</updated>
<author>
<name>Raviteja Laggyshetty</name>
<email>raviteja.laggyshetty@oss.qualcomm.com</email>
</author>
<published>2026-06-03T11:26:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b148c1f785f3a641fa58a23da5f344a0dfa038a1'/>
<id>b148c1f785f3a641fa58a23da5f344a0dfa038a1</id>
<content type='text'>
Add Epoch Subsystem (EPSS) L3 interconnect provider support on
Qualcomm Shikra SoC.

The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM
L3 providers, but supports only up to 12 frequency lookup table entries.
Reading beyond the supported LUT entries can expose incorrect frequencies.
Add shikra-specific EPSS descriptor shikra_epss_l3_perf_state that reuses
existing EPSS configuration with appropriate LUT entries limit.

Co-developed-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-2-3c2e0b796e78@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add Epoch Subsystem (EPSS) L3 interconnect provider support on
Qualcomm Shikra SoC.

The EPSS L3 block on Shikra SoC is similar to existing Qualcomm EPSS/OSM
L3 providers, but supports only up to 12 frequency lookup table entries.
Reading beyond the supported LUT entries can expose incorrect frequencies.
Add shikra-specific EPSS descriptor shikra_epss_l3_perf_state that reuses
existing EPSS configuration with appropriate LUT entries limit.

Co-developed-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Signed-off-by: Odelu Kukatla &lt;odelu.kukatla@oss.qualcomm.com&gt;
Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260603-shikra_epss_l3-v3-2-3c2e0b796e78@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'icc-x1e80100' into icc-next</title>
<updated>2026-07-07T13:32:56+00:00</updated>
<author>
<name>Georgi Djakov</name>
<email>djakov@kernel.org</email>
</author>
<published>2026-07-07T13:32:56+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=3b828034ad9e2976f3f0cdc4fa25ec727ff23c70'/>
<id>3b828034ad9e2976f3f0cdc4fa25ec727ff23c70</id>
<content type='text'>
This series enables QoS configuration for QNOC type device which
can be found on X1E80100 platform. It enables QoS configuration
for master ports with predefined priority and urgency forwarding.
This helps in prioritizing the traffic originating from different
interconnect masters at NOC (Network On Chip).

The system may function normally without this feature. However,
enabling QoS helps optimize latency and bandwidth across subsystems
like CPU, GPU, and multimedia engines, which becomes important in
high-throughput scenarios. This is a feature aimed at performance
enhancement to improve system performance under concurrent workloads.

* icc-x1e80100
  dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS
  interconnect: qcom: x1e80100: enable QoS configuration

Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This series enables QoS configuration for QNOC type device which
can be found on X1E80100 platform. It enables QoS configuration
for master ports with predefined priority and urgency forwarding.
This helps in prioritizing the traffic originating from different
interconnect masters at NOC (Network On Chip).

The system may function normally without this feature. However,
enabling QoS helps optimize latency and bandwidth across subsystems
like CPU, GPU, and multimedia engines, which becomes important in
high-throughput scenarios. This is a feature aimed at performance
enhancement to improve system performance under concurrent workloads.

* icc-x1e80100
  dt-bindings: interconnect: qcom,x1e80100-rpmh: add clocks property to enable QoS
  interconnect: qcom: x1e80100: enable QoS configuration

Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-0-305c6539e6d2@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>interconnect: qcom: x1e80100: enable QoS configuration</title>
<updated>2026-07-07T13:32:10+00:00</updated>
<author>
<name>Raviteja Laggyshetty</name>
<email>raviteja.laggyshetty@oss.qualcomm.com</email>
</author>
<published>2026-05-27T05:37:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=5a8b2cc36e796d595c9d97eab23c2be22805cc1c'/>
<id>5a8b2cc36e796d595c9d97eab23c2be22805cc1c</id>
<content type='text'>
Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-2-305c6539e6d2@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Reviewed-by: Konrad Dybcio &lt;konrad.dybcio@oss.qualcomm.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@oss.qualcomm.com&gt;
Signed-off-by: Raviteja Laggyshetty &lt;raviteja.laggyshetty@oss.qualcomm.com&gt;
Link: https://patch.msgid.link/20260527-x1e80100_qos-v2-2-305c6539e6d2@oss.qualcomm.com
Signed-off-by: Georgi Djakov &lt;djakov@kernel.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
