linux-stable.git/drivers/i3c, branch master

i3c: dw: reduce do_daa time if there's no client

2026-08-19T07:28:33+00:00

dw_i3c_master_daa() derives the number of newly assigned dynamic
addresses from cmd->rx_len, the ISR sets it to the number of address
slots ENTDAA left unassigned. It starts out as zero, which already
means "every address was assigned", so a timed out transfer leaves
that value in place and it gets used as a result.

If there's no client connected, the addr assign cmd times out, then
the driver calls i3c_master_add_i3c_dev_locked() to add devices that
are not there, each costing about 1s, thus adds non necessary boot
time up to (maxdev * 1)s.

Start from maxdevs instead: no address is assigned before ENTDAA runs,
and the existing rx_count >= maxdevs check then reports an empty bus.

Signed-off-by: Jisheng Zhang 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260819044833.32611-1-jszhang@kernel.org
Signed-off-by: Alexandre Belloni

i3c: mipi-i3c-hci: Add support for AMD_PT I3C controller

2026-08-18T21:19:34+00:00

Add support for the AMD_PT I3C controller by introducing the following
changes:
- Add AMD_PT I3C controller platform device ID in core.c.
- Register AMD_PT I3C controller PCI ID in mipi-i3c-hci-pci.c.

Co-developed-by: Patrick Yen 
Signed-off-by: Patrick Yen 
Signed-off-by: Jian-Ming Liao 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260818104106.763772-4-Jm_Liao@asmedia.com.tw
Signed-off-by: Alexandre Belloni

i3c: mipi-i3c-hci: Add PIO queue management support for HCI v1.2

2026-08-18T21:19:34+00:00

Support explicit enablement and starting of PIO queues as required by
HCI v1.2.
Handle alternate PIO queue sizes via ALT_QUEUE_SIZE register.
Implement explicit PIO queue stopping/disabling and restart logic after
errors.

Co-developed-by: Patrick Yen 
Signed-off-by: Patrick Yen 
Signed-off-by: Jian-Ming Liao 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260818104106.763772-3-Jm_Liao@asmedia.com.tw
Signed-off-by: Alexandre Belloni

i3c: mipi-i3c-hci: Fix missing STAT_IBI_STATUS_THLD in PIO mode

2026-08-18T21:19:34+00:00

In PIO mode initialization, STAT_IBI_STATUS_THLD was missing from
pio->enabled_irqs. As a result, the host controller interrupt signal for
IBI threshold was never enabled when transfer starts, preventing IBI
status descriptors from being properly processed in PIO mode.

Include STAT_IBI_STATUS_THLD in pio->enabled_irqs so that the IBI
threshold interrupt is activated alongside error interrupts upon the first
transfer.

Fixes: 9ad9a52cce28 ("i3c/master: introduce the mipi-i3c-hci driver")
Co-developed-by: Patrick Yen 
Signed-off-by: Patrick Yen 
Signed-off-by: Jian-Ming Liao 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260818104106.763772-2-Jm_Liao@asmedia.com.tw
Signed-off-by: Alexandre Belloni

i3c: dw: rename "pclk" to "apb" to match dt-binding

2026-08-18T21:15:51+00:00

Change clock name "pclk" to "apb" to match dt-binding doc. No upstream
device tree sources currently use the "pclk" clock name, so no any
backward compatibility issues.

Fixes: a0d48ebf39ce ("i3c: dw: Add optional apb clock")
Signed-off-by: Jisheng Zhang 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260814040345.23033-1-jszhang@kernel.org
Signed-off-by: Alexandre Belloni

i3c: dw: make struct dw_i3c_cmd smaller

2026-08-18T21:02:38+00:00

The dw_i3c_cmd is dynamically allocated, make it smaller. For example
on 64bit platforms, we reduce the size from 48 bytes to 32 bytes.

Signed-off-by: Jisheng Zhang 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260813044603.22425-1-jszhang@kernel.org
Signed-off-by: Alexandre Belloni

i3c: dw: use COMMAND_PORT_TRANSFER_ARG instead of hardcoding

2026-08-18T21:02:15+00:00

Use the well defined COMMAND_PORT_TRANSFER_ARG macro instead of
hardcoding '1'.

Signed-off-by: Jisheng Zhang 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260813044225.22237-1-jszhang@kernel.org
Signed-off-by: Alexandre Belloni

i3c: renesas: Don't register devices when ENTDAA times out

2026-08-08T13:12:39+00:00

renesas_i3c_daa() derives the number of newly assigned dynamic addresses
from cmd->rx_count, which the response ISR sets to the number of address
slots ENTDAA left unassigned. It starts out as zero, which already means
"every address was assigned", so a timed out transfer leaves that value
in place and it gets used as a result.

On a bus with no target connected the ENTDAA times out and the driver
registers RENESAS_I3C_MAX_DEVS devices that are not there, each costing
the core two seconds on a GETPID that can only time out:

  i3c i3c-0: Failed to add I3C device at address 9, error -110
  ...
  i3c i3c-0: Failed to add I3C device at address 16, error -110

Start from maxdevs instead: no address is assigned before ENTDAA runs,
and the existing rx_count >= maxdevs check then reports an empty bus.

Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
Signed-off-by: Tommaso Merciai 
Reviewed-by: Claudiu Beznea 
Tested-by: Claudiu Beznea  # on RZ/G3S
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260731070150.2519825-1-tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Alexandre Belloni

i3c: master: dw-i3c-master: fix OD timing for first broadcast

2026-08-08T13:10:34+00:00

Implement ->set_speed() so the I3C core can switch open-drain timing for
the first broadcast address per spec: I3C_OPEN_DRAIN_SLOW_SPEED programs
tHIGH_INIT (200 ns) before RSTDAA, and I3C_OPEN_DRAIN_NORMAL_SPEED restores
normal OD timing afterward. Cache the normal OD register value during bus
init and use a separate od_hcnt for the slow path so SDR extended timing
remains derived from the normal PP hcnt.

For AMD_I3C_OD_PP_TIMING, cache AMD_I3C_OD_TIMING as the normal OD
baseline and stop rewriting OD timing in send_ccc_cmd()/runtime resume so
I3C_OPEN_DRAIN_SLOW_SPEED is preserved through RSTDAA.

Use PM_RUNTIME_ACQUIRE_AUTOSUSPEND() in set_speed(). Compute od_hcnt with
DIV_ROUND_UP_ULL() for 32-bit safety and clamp it to U8_MAX to match the
8-bit I3C_OD_HCNT field.

Fixes I2C devices with spike filters not being detected on mixed buses.

Signed-off-by: Tze Yee Ng 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/d789219ca0418898a1ef2bf9295b4f96ca7b4209.1785484707.git.tze.yee.ng@altera.com
Signed-off-by: Alexandre Belloni

i3c: mipi-i3c-hci: Advertise IBI wakeup capability

2026-08-08T13:04:20+00:00

Set master->ibi_wakeup during probe when the associated system device
advertises wakeup capability, allowing the I3C core to mark IBI-capable
I3C devices as wakeup capable.

Tweak the comment for i3c_hci_sysdev() to mention the new usage.

Signed-off-by: Adrian Hunter 
Reviewed-by: Frank Li 
Link: https://patch.msgid.link/20260807145638.168865-15-adrian.hunter@intel.com
Signed-off-by: Alexandre Belloni